AD5313 datasheet(14/20 Pages) AD

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AD5332/AD5333/AD5342/AD5343

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PARALLEL INTERFACE

The AD5332, AD5333, and AD5342 load their data as a single

8-, 10-, or 12-bit word, while the AD5343 loads data as a low

byte of 8 bits and a high byte containing 4 bits.

Double-Buffered Interface

The AD5332/AD5333/AD5342/AD5343 DACs all have double-

buffered interfaces consisting of an input register and a DAC

input register under control of the Chip Select (CS) and Write

(WR).

Access to the DAC register is controlled by the LDAC function.

When LDAC is high, the DAC register is latched and the input

DAC register. However, when LDAC is brought low, the DAC

are also double-buffered and are only updated when LDAC is

taken low.

This is useful if the user requires simultaneous updating of all

DACs and peripherals. The user may write to both input regis-

ters individually and then, by pulsing the LDAC input low, both

outputs will update simultaneously.

Double-buffering is also useful where the DAC data is loaded in

two bytes, as in the AD5343, because it allows the whole data

word to be assembled in parallel before updating the DAC register.

This prevents spurious outputs that could occur if the DAC

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that LDAC was brought low. Normally, when

LDAC is brought low, the DAC registers are filled with the

contents of the input registers. In the case of the AD5332/

AD5333/AD5342/AD5343, the part will only update the DAC

time the DAC register was updated. This removes unnecessary

crosstalk.

Clear Input (CLR)

CLR is an active low, asynchronous clear that resets the input and

DAC registers.

Chip Select Input (CS)

CS is an active low input that selects the device.

Write Input (WR)

WR is an active low input that controls writing of data to the

device. Data is latched into the input register on the rising edge

of WR.

Load DAC Input (LDAC)

LDAC transfers data from the input register to the DAC register

(and hence updates the outputs). Use of the LDAC function enables

double buffering of the DAC data, GAIN and BUF. There are

two LDAC modes:

Synchronous Mode: In this mode the DAC register is updated

after new data is read in on the rising edge of the WR input.

LDAC can be tied permanently low or pulsed as in Figure 1.

Asynchronous Mode: In this mode the outputs are not updated

at the same time that the input register is written to. When LDAC

goes low the DAC register is updated with the contents of the

input register.

Resistor String

The resistor string section is shown in Figure 29. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at what node on the string the

voltage is tapped off to be fed into the output ampliﬁer. The

voltage is tapped off by closing one of the switches connecting

the string to the ampliﬁer. Because it is a string of resistors, it

is guaranteed monotonic.

TO OUTPUT

AMPLIFIER

VREF

Figure 29. Resistor String

DAC Reference Input

The DACs operate with an external reference. The AD5332,

AD5333, and AD5342 have separate reference inputs for each

DAC, while the AD5343 has a single reference input for both

DACs. The reference inputs on the AD5333 and AD5342 may

be configured as buffered or unbuffered. The reference inputs

of the AD5332 and AD5343 are unbuffered. The buffered/

unbuffered option is controlled by the BUF pin.

In buffered mode (BUF = 1) the current drawn from an exter-

nal reference voltage is virtually zero, as the impedance is at

least 10 M

Ω. The reference input range is 1 V to V

DD.

In unbuffered mode (BUF = 0) the user can have a reference

voltage as low as 0.25 V and as high as VDD since there is no

restriction due to headroom and footroom of the reference ampli-

fier. The impedance is still large at typically 180 k

Ω for 0–V

REF

mode and 90 k

Ω for 0–2 VREF mode.

If using an external buffered reference (e.g., REF192) there is

no need to use the on-chip buffer.

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating output volt-

ages to within 1 mV of either rail. Its actual range depends on

VREF, GAIN, the load on VOUT and offset error.

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V

to VREF.

If a gain of 2 is selected (GAIN = 1), on the AD5333 and AD5342

the output range is 0.001 V to 2 VREF.

The output ampliﬁer is capable of driving a load of 2 k

Ω to

GND or VDD, in parallel with 500 pF to GND or VDD. The

source and sink capabilities of the output ampliﬁer can be seen

in Figure 15.

The slew rate is 0.7 V/

µs with a half-scale settling time to ±0.5 LSB

(at 8 bits) of 6

µs with the output unloaded. See Figure 20.

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