AD664 datasheet(12/20 Pages) AD

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AD664

REV. C

–12–

Output Loads

Readback timing is tested with the output loads shown in Figure

22.

Figure 22. Output Loads

Asynchronous Reset Operation

The asynchronous reset signal shown in Figure 23 may be

asserted at any time. A minimum pulse width (tRW) of 90 ns is

required. The reset feature is designed to return all DAC out-

puts to 0 volts regardless of the mode or range selected. In the

44-pin versions, the modes are reset to unipolar 10 V span (gain

of 1), and the input codes are rewritten to be “0s.” Previous

DAC code and mode information is erased.

Figure 23a. Asynchronous Reset Operation

Figure 23b. Asynchronous Reset Operation Timing

In the 28-pin versions of the AD664, the mode remains

unchanged, the appropriate input code is rewritten to reset the

output voltage to 0 volts. As in the 44-pin versions, the previous

input data is erased.

At power-up, an AD664 may be activated in either the read or

write modes. While at the device level this will not produce any

problems, at the system level it may. Analog Devices recom-

mends the addition of a simple power-on reset scheme to any

system where the possibility of an unknown start-up state could

be a problem. The simplest version of this scheme is illustrated

in Figure 24.

AD664

+5V

10k

Ω

100nF

RST

Figure 24. Power-On Reset

It is obvious from inspection that the scheme shown in Figure

24 is only appropriate for systems in which the RST is otherwise

not used. Should the user wish to use the RST pin, an addi-

tional logic gate may be included to combine the power-on reset

with the reset signal.

INTERFACING THE AD664 TO MICROPROCESSORS

The AD664 is easy to interface with a wide variety of popular

microprocessors. Common architectures include processors with

dedicated 8-bit data and address buses, an 8-bit bus over which

data and address are multiplexed, an 8-bit data and 16-bit

address partially muxed, and separate 16-bit data and address

buses.

AD664 addressing can be accomplished through either

memory-mapped or I/O techniques. In memory-mapped

schemes, the AD664 appears to the host microprocessor as

RAM memory. Standard memory addressing techniques are

used to select the AD664. In the I/O schemes, the AD664 is

treated as an external I/O device by the host. Dedicated I/O pins

are used to address the AD664.

MC6801 Interface

In Figures 25a–25d, we illustrate a few of the various methods

that can be used to connect an AD664 to the popular MC6801

microprocessor. In each of these cases, the MC6801 is intended

to be configured in its expanded, nonmultiplexed mode of

operation. In this mode, the MC6801 can address 256 bytes of

external memory over 8-bit data (Port 3) and 8-bit address

(Port 4) buses. Eight general-purpose I/O lines (Port 1) are also

available. On-board RAM and ROM provide program and data

storage space.

In Figure 25a, the three least significant address bits (P40, P41

and P42) are employed to select the appropriate on-chip

addresses for the various input registers of the AD664. Three

I/O lines (P17, P16 and P15) are used to select various operat-

ing features of the the AD664. IOS and E(nable) are combined

to produce an appropriate CS signal. This addressing scheme

leaves the five most significant address bits and five I/O lines

free for other tasks in the system.

Figure 25b shows another way to interface an AD664 to the

MC6801. Here we’ve used the six least significant address lines

to select AD664 features and registers. This is a purely memory-

mapped scheme while the one illustrated in Figure 25a uses

some memory-mapping as well as some dedicated I/O pins. In

Figure 25b, two address lines and all eight I/O lines remain free

for other system tasks.

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