AD664 datasheet(14/20 Pages) AD

14 / 20 page

AD664

REV. C

–14–

The schemes in Figure 25 illustrate some of the trade-offs which

a designer may make when configuring a system. For example,

the designer may use I/O lines instead of address bits or vice

versa. This decision may be influenced by other I/O tasks or sys-

tem expansion requirements. He/she can also choose to imple-

ment only a subset of the features available. Perhaps the RST

pin isn’t really needed. Tying that input pin to VLOGIC frees up

another I/O or address bit. The same consideration applies to

mode select. In all of these cases TR is shown tied to VLOGIC,

because the MC6801 cannot provide the 12-bit-wide input

word required for the transparent mode. In situations where

transparent operation isn’t required, and mode select is also not

needed, the designer may consider specifying the DIP version of

the device (either the UNI or BIP version).

Each of the schemes illustrated in Figure 25 operates with an

MC6801 at clock rates up to and including 1.5 MHz. Similar

schemes can be derived for other 8-bit microprocessors and

microcontrollers such as the 8051/8086/8088/6502, etc. One

such scheme developed for the 8051/AD664 is illustrated in

Figure 26.

8051 Interface

Figure 26 shows the AD664 combined with an 8051

µcontroller

chip. Three LSBs of address provide the quad and DAC select

signals. Control signals from Port 1 select various operating

modes such as readback, mode select and reset as well as pro-

viding the LS signal. Read and write signals from the 8051 are

decoded to provide the CS signal.

Figure 25d. Interfacing Eight AD664s to an MC6801

AD664 Datasheet(PDF) 14 Page - Analog Devices