AD677

REV. A

–6–

PIN DESCRIPTION

DIP Pin

SOIC Pin

Type

Name

Description

1

1

SAMPLE

DI

controls the suite of the internal sample-hold amplifier and the falling edge

initiates conversion. During calibration, SAMPLE should be held LOW. If

HIGH during calibration, diagnostic information will appear on SDATA.

2

2

CLK

DI

Master Clock Input. The AD677 requires 17 clock pulses to execute a

conversion. CLK is also used to derive SCLK.

3

3

SDATA

DO

Serial Output Data Controlled by SCLK.

4

6, 7

DGND

P

Digital Ground.

58

P

+12 V Analog Supply Voltage.

8

12

AGND

P

Analog Ground.

.9

15

AGND SENSE

AI

Analog Ground Sense.

10

16

AI

Analog Input Voltage.

11

17

AI

External Voltage Reference Input.

12

21

P

–12 V Analog Supply Voltage.

13

22, 23

P

+5 V Logic Supply Voltage.

14

26

SCLK

DO

Clock Output for Data Read, derived from CLK.

15

27

BUSY

DO

Status Line for Converter. Active HIGH, indicating a conversion or

calibration in progress.

16

28

CAL

DI

Calibration Control Pin.

6, 7

4, 5, 9, 10, 11,

NC

_

No Connection. No connections should be made to these pins.

13, 14, 18, 19,

20, 24, 25

Type: AI = Analog Input

DI = Digital Input

DO = Digital Output

P = Power

1

2

3

7

28

27

26

22

8

9

10

21

20

19

11

12

18

17

4

5

25

24

6

23

TOP VIEW

(Not to Scale)

13

14

16

15

AD677

NC = NO CONNECT

NC

AGND

CLK

SAMPLE

DGND2

NC

NC

NC

NC

NC

SDATA

DGND1

NC

CAL

BUSY

NC

NC

NC

NC

NC

SCLK

AGND

SENSE

SOIC Pinout

SAMPLE

CLK

DGND

NC

NC

AGND

CAL

BUSY

AGND

SENSE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

TOP VIEW

(Not to Scale)

AD677

NC = NO CONNECT

SCLK

SDATA

DIP Pinout