AD7002

–11–

REV. B

from the analog modulator, will the output data be correct. The

analog modulator, on coming out of sleep, will generate mean-

ingful data after 21 master clock cycles.

01...111

01...110

00...001

00...000

11...111

11...110

10...001

10...000

–V

FULLSCALE

+V

FULLSCALE

V

REF

V

Figure 13. ADC Transfer Function for I and Q Receive

Channels

Calibration

Included in the digital filter is a means by which receive signal

offsets may be calibrated out. Calibration can be effected

through the use of the CAL and MZERO pins.

Each channel of the digital low-pass filter section has an offset

register. The offset register can be made to contain a value

representing the dc offset of the preceding analog circuitry. In

normal operation, the value stored in the offset register is sub-

tracted from the filter output data before the data appears on

the serial output pin. By so doing, the dc offset is cancelled.

In each channel the offset register is cleared (twos complement

zero) when CAL is high and becomes loaded with the first digi-

tal filter result after CAL falls. This result will be a measure of

the channel dc offset if the analog channel is switched to zero

prior to CAL falling. Time must be provided for the analog

circuitry and the digital filter to settle after the analog circuitry is

switched to zero and before CAL falls. The offset register will

then be loaded with the proper representation of the dc offset.

CAL must be high for more than 608 master clock cycles

(CLK1, CLK2). If the analog channels are switched to zero

coincident with CAL rising, this time is also sufficient to satisfy

the settling time of the analog sigma-delta modulators and the

digital filters. CAL may be held high for an unlimited time if

convenient or necessary. Only the digital result following the fall

of CAL will be loaded into each offset register. After CAL falls,

normal operation resumes immediately.

10.00

–140.00

1000

–100.00

–120.00

100

0

–80.00

–50.00

–30.00

–10.00

900

800

700

600

500

400

300

200

0.00

–110.00

–130.00

–70.00

–90.00

–60.00

–40.00

–20.00

FREQUENCY – kHz

Figure 14. Digital Filter Frequency Response

The offset registers are static and retain their contents even

need only be updated if drifts in the analog dc offsets are experi-

enced or expected. However, on initial application of power to

the digital supply pins the offset registers may contain grossly

incorrect values and, therefore, calibration must be activated at

least once after power is applied even if the facility of calibration

is not regularly used.

Table II. Truth Table for the MODE and RATE Pins

MODE

RATE

Data Format

Output Word Rate

0

0

IQ Data

I/

Q

270.8 kHz

0

1

IQ Data

I/

Q

541.7 kHz

1

0

I Data

Q Data

270.8 kHz

1

1

I Data

Q Data

541.7 kHz

The MZERO pin can be used to zero the sigma-delta modula-

tors if calibration of preceding analog circuitry is not required.

Each analog modulator has an internal analog multiplexer con-

trolled by MZERO. With MZERO low, the modulator inputs

are connected to the I Rx and Q Rx pins for normal operation.

With MZERO high, both modulator inputs are connected to the

tion of external analog circuitry is desired, MZERO should be

kept low during the calibration cycle.

Rx SLEEP1

Rx SLEEP2

CAL

RATE, MODE,

THREE- STATE

CONTROL

t

39

t

38

40

t

Figure 15. Calibration and Control Timing Diagram