AD7002

–12–

REV. B

The offset registers have enough resolution to hold the value of

any dc offset between

±5 V. However, the performance of the

sigma-delta modulators will degrade if full scale signals with

more than 100 mV of offset are experienced. If large offsets are

present, these can be calibrated out, but signal excursions from

the offsets should be limited to keep the I Rx and Q Rx voltages

within

±1.35 V of V

Receive Section Digital Interface

A flexible serial interface is provided for the AD7002 receive

section. Four basic operating modes are available. Table II

shows the truth table for the different serial modes available.

The MODE pin determines whether the I and Q serial data is

made available on two separate pins (MODE 1) or combined

onto a single output pin (MODE 0). The RATE pin determines

whether I and Q receive data is provided at 541.7 kHz (RATE 1)

or at 270.8 kHz (RATE 0).

When the receive section is put into sleep mode, by bringing

complete the current IQ cycle before entering into a low power

sleep mode.

MODE 0 RATE I Interface

The timing diagram for the MODE 0 RATE 1 receive interface

is shown in Figure 16. It can be used to interface to DSP pro-

cessors requiring only one serial port.

When using MODE 0, the serial data is made available on the

Rx DATA pin, with the I/

Q pin indicating whether the 12-bit

word being clocked out is an I sample or a Q sample. Although

the I data is clocked out before the Q data, internally both

samples are processed together. RATE 1 selects an output word

rate of 541.7 kHz, which is equal to the master clock (CLK1,

CLK2) divided by 24.

When the receive section is brought out of sleep mode, by bring-

cycles) the Rx CLK output will continuously shift out I and Q

data, always beginning with I data. Rx SYNC provides a fram-

ing signal used to indicate the beginning of an I or Q, 12-bit

data word that is valid on the next falling edge of Rx CLK. On

coming out of sleep, Rx SYNC goes high one clock cycle before

the beginning of I data, and subsequently goes high in the same

clock cycle as the last bit of each 12-bit word (both I and Q). Rx

DATA is valid on the falling edge of Rx CLK and is clocked out

MSB first, with the I/

Q pin indicating whether Rx DATA is I

data or Q data.

MODE 0 RATE 0 Interface

Figure 17 shows the receive timing diagram when MODE 0,

RATE 0 is selected. Again I and Q data are shifted out on the

Rx DATA pin, but here the output word rate is reduced to

270.8 kHz, this being equal to master clock (CLK1, CLK2)

divided by 48.

Once the receive section is brought out of sleep mode, (after 56

master clock cycles) the Rx CLK output becomes active and

generates an Rx SYNC framing pulse on the first Rx CLK.

This is followed by 12 continuous clock cycles during which the

I data is shifted out on the Rx DATA pin. Following this the

Rx CLK remains high for 11 master clock cycles before clocking

out the Q data in exactly the same manner.

Rx DATA is valid on the falling edge of Rx CLK with the I/

Q

pin indicating whether Rx DATA is I data or Q data.

MODE 1 RATE I Interface

Figure 18 shows the timing for MODE 1 RATE 1 receive digital

interface. MODE 1 RATE 1 gives an output word rate of

541.7 kHz, but I and Q data are transferred on separate pins.

I data is shifted out on Rx DATA (IDATA) pin and Q data is

shifted out on the I/

Q (QDATA) pin. RATE 1 selects an output

word rate of 541.7 kHz (this is equal to the master clock divided

by 24).

When the receive section is brought out of sleep mode, by bring-

cycles), the Rx CLK output will continuously shift out I and Q

data, on separate pins. Rx SYNC provides a framing signal used

to indicate the beginning of an I or Q, 12-bit data word that

is valid on the next falling edge of Rx CLK. On coming out

of sleep, Rx SYNC goes high one clock cycle before the begin-

ning of I data, and subsequently goes high in the same clock

cycle as the I and Q LSBs. It takes 24 Rx CLKs (excluding the

first framing pulse) to complete a single IQ cycle. IDATA and

QDATA are valid on the falling edge of Rx CLK and are

clocked out MSB first.

MODE I RATE 0 Interface

Figure 19 shows the receive timing diagram when MODE 1

RATE 0 is selected. MODE 1 RATE 0, again I and Q data are

transferred on separate pins. I data is shifted out on Rx DATA

(IDATA) pin and Q data is shifted out on the I/

Q (QDATA)

pin. The output word rate is reduced to 270.8 kHz, this equal to

master clock (CLK1, CLK2) divided by 48.

Once the receive section is brought out of sleep mode, and after

56 master clock cycles, the Rx CLK output becomes active and

generates an Rx SYNC framing pulse on the first Rx CLK. This

is followed by 12 continuous clock cycles during which both the

I and Q data is shifted out on IDATA and QDATA pins. Fol-

lowing this the Rx CLK remains high for 22 master clock cycles

before clocking out the next IQ data pair.