AD7002

–15–

REV. B

PIN FUNCTION DESCRIPTIONS

PQFP Pin

Number

Mnemonic

Function

POWER SUPPLY

37

Positive power supply for analog section. This is +5 V

± 10%.

38

AGND

Analog ground.

4, 15

Positive power supply for digital section. This is +5 V

± 10%.

5, 16

DGND

Digital ground.

ANALOG SIGNAL AND REFERENCE

41

I Tx

Analog output for the I (In-Phase) channel. This output comes from a 10-bit DAC and is

filtered by a Bessel low pass filter. The 10-bit DAC is loaded with I data, which is generated

by the GMSK modulator.

39

Q Tx

Analog output for the Q (Quadrature) channel. This output comes from a 10-bit DAC and is

filtered by a Bessel low pass filter. The 10-bit DAC is loaded with Q data, which is generated

by the GMSK modulator.

44

I Rx

Analog input for I receive channel.

42

Q Rx

Analog input for Q receive channel.

34

AUX DAC1

Analog output voltage from the 9-bit auxiliary DAC. This is a voltage mode DAC with a high

output impedance and hence should be buffered if used to drive moderate impedance loads.

36

AUX DAC2

Analog output voltage from the 10-bit auxiliary DAC. This is a voltage mode DAC with a

high output impedance and hence should be buffered if used to drive moderate impedance

loads.

35

AUX DAC3

Analog output voltage from the 8-bit auxiliary DAC. This is a voltage mode DAC with a high

output impedance and hence should be buffered if used to drive moderate impedance loads.

40

REFOUT

Reference output; this is 2.48 volts nominal.

TRANSMIT INTERFACE AND CONTROL

7, 11

CLK1, CLK2

Master clock inputs for both the transmit and receive sections. CLK1 and CLK2 must be

externally hardwired together and driven from a 13 MHz TTL compatible crystal.

3

Tx CLK

Clock output from the AD7002 which can be used to clock in the data for the transmit section.

2

Tx DATA

Data input for the transmit section, data is clocked on the falling edge of Tx CLK.

1

Tx SLEEP

Sleep control input for transmit section. When it is high, the transmit section goes into

standby mode and draws minimal current.

RECEIVE INTERFACE AND CONTROL

13

MODE

Digital control input. When High (MODE 1), the I and Q outputs are on separate pins

(QDATA and IDATA). When Low (MODE 0), I and Q are on the same pin (Rx DATA).

12

RATE

Digital control input. This determines whether the receive section interface operates at a

word rate of 541.7 kHz or at a word rate of 270.8 kHz. When High (RATE 1), the output

word rate is 541.7 kHz. When Low (RATE 0), the output word rate is 270.8 kHz.

18

Rx DATA (IDATA) This is a dual function digital output. When the device is operating in MODE 0, the Rx

DATA (both I and Q) is available at this pin. When the device is operating in MODE 1, only

IDATA is available at this pin.

VOLTAGE REFERENCE

The AD7002 contains an on-chip bandgap reference that pro-

vides a low noise, temperature compensated reference to the IQ

transmit DACs and the IQ receive ADCs. The reference is also

made available on the REFOUT pin and can be used to bias

other analog circuitry in the IF section.

When both the transmit section and the receive section are in

sleep mode (Tx SLEEP and Rx SLEEP asserted), the reference

output buffer is also powered down by approximately 80%

compatible crystal.

AUX CLK (I)

AUX DATA (I)

AUX LATCH (I)

AUX FLAG (O)

DB15

DB14

DB1

DB0

t

20

t

16

NEW AUX FLAG

OLD AUX FLAG

Figure 22. Auxiliary DAC Timing Diagram