AD73322AST datasheet(6/43 Pages) AD

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AD73322

–6–

REV. B

AD73322A

arameter

Min

Typ

Max

Units

Test Conditions/Comments

DIGITAL GAIN TAP

Gain at Maximum Setting

Gain at Minimum Setting

–1

Gain Resolution

Bits

Tested to 5 MSBs of Settings

Delay

µs

Includes DAC Delay

Settling Time

100

µs

Tap Gain Change from –FS to +FS; Includes

DAC Settling Time

DAC SPECIFICATIONS

5VEN = 1

Maximum Voltage Output Swing

Single-Ended

3.156

V p-p

PGA = 6 dB

3.17

dBm

Max Output = (3.156/2.4)

× VREFCAP

Differential

6.312

V p-p

PGA = 6 dB

9.19

dBm

Max Output = 2

× ([3.156/2.4] × VREFCAP)

Nominal Voltage Output Swing (0 dBm0)

Single-Ended

2.1908

V p-p

PGA = 6 dB

dBm

Differential

4.3918

V p-p

PGA = 6 dB

6.02

dBm

Output Bias Voltage

2.4

REFOUT Unloaded

Absolute Gain

+0.4

1.0 kHz, 0 dBm0; Unloaded

Gain Tracking Error

±0.1

1.0 kHz, +3 dBm0 to –50 dBm0

Signal to (Noise + Distortion) at 0 dBm0

Refer to Figure 8

PGA = 6 dB

300 Hz to 3400 Hz; fSAMP = 64 kHz

Total Harmonic Distortion at 0 dBm0

PGA = 6 dB

–80

300 Hz to 3400 Hz; fSAMP = 64 kHz

Intermodulation Distortion

–85

PGA = 0 dB

Idle Channel Noise

–85

dBm0

PGA = 0 dB

Crosstalk

DAC-to-ADC

–90

ADC Input Signal Level: AGND; DAC

Output Signal Level: 1.0 kHz, 0 dBm0;

Input Amplifiers Bypassed

–77

Input Amplifiers Included In Input Channel

DAC-to-DAC

–100

DAC1 Output Signal Level: AGND; DAC2

Output Signal Level: 1.0 kHz, 0 dBm0

Power Supply Rejection

–65

Input Signal Level at AVDD and DVDD

Pins: 1.0 kHz, 100 mV p-p Sine Wave

Group Delay

4, 5

µs

Interpolator Bypassed

µs

Output DC Offset

2, 7

+12

Minimum Load Resistance, RL

2, 8

Single-Ended

150

Ω

Differential

150

Ω

Maximum Load Capacitance, CL

2, 8

Single-Ended

500

Differential

100

FREQUENCY RESPONSE

(ADC and DAC)

9 Typical Output

Frequency (Normalized to FS)

0.03125

–0.1

0.0625

–0.25

0.125

–0.6

0.1875

–1.4

0.25

–2.8

0.3125

–4.5

0.375

–7.0

0.4375

–9.5

> 0.5

< –12.5

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