AD73322AST datasheet(8/43 Pages) AD

8 / 43 page

AD73322

–8–

REV. B

Table III. Signal Ranges

3 V Power Supply

5 V Power Supply

5VEN = 0

5VEN = 1

VREFCAP

1.2 V

± 10%

1.2 V

2.4 V

VREFOUT

1.2 V

± 10%

1.2 V

2.4 V

ADC

Maximum Input Range

at VIN

1.578 V p-p

3.156 V p-p

Nominal Reference Level

1.0954 V p-p

2.1908 V p-p

DAC

Maximum Voltage

Output Swing

Single-Ended

1.578 V p-p

3.156 V p-p

Differential

3.156 V p-p

6.312 V p-p

Nominal Voltage

Output Swing

Single-Ended

1.0954 V p-p

2.1908 V p-p

Differential

2.1909 V p-p

4.3818 V p-p

Output Bias Voltage

VREFOUT

TIMING CHARACTERISTICS

Limit at

Parameter

TA = –40 C to +85 C

Units

Description

Clock Signals

See Figure 1

ns min

MCLK Period

24.4

ns min

MCLK Width High

24.4

ns min

MCLK Width Low

Serial Port

See Figures 3 and 4

ns min

SCLK Period

0.4

× t

ns min

SCLK Width High

0.4

× t

ns min

SCLK Width Low

ns min

SDI/SDIFS Setup Before SCLK Low

ns min

SDI/SDIFS Hold After SCLK Low

ns max

SDOFS Delay from SCLK High

t10

ns min

SDOFS Hold After SCLK High

t11

ns min

SDO Hold After SCLK High

t12

ns max

SDO Delay from SCLK High

t13

ns max

SCLK Delay from MCLK

Specifications subject to change without notice.

(AVDD = +3 V

10%; DVDD = +3 V

10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless

otherwise noted)

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