AD73360ASU datasheet(15/35 Pages) AD

15 / 35 page

REV. A

AD73360

–15–

Table VII. Control Register A Description

654321

RESET

DC2

DC1

DC0

SLB

–

DATA/

PGM

Bit Name

Description

DATA/

PGM

Operating Mode (0 = Program; 1 = Data Mode)

Mixed Mode (0 = OFF; 1 = Enabled)

Reserved

Must Be Programmed to Zero (0)

SLB

SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)

DC0

Device Count (Bit 0)

DC1

Device Count (Bit 1)

DC2

Device Count (Bit 2)

RESET

Software Reset (0 = OFF; 1 = Initiates Reset)

Table VIII. Control Register B Description

76543210

C E E

MCD2

MCD1

MCD0

SCD1

SCD0

DR1

DR0

Bit Name

Description

DR0

Decimation Rate (Bit 0)

DR1

Decimation Rate (Bit 1)

SCD0

Serial Clock Divider (Bit 0)

SCD1

Serial Clock Divider (Bit 1)

MCD0

Master Clock Divider (Bit 0)

MCD1

Master Clock Divider (Bit 1)

MCD2

Master Clock Divider (Bit 2)

CEE

Control Echo Enable (0 = OFF; 1 = Enabled)

Table IX. Control Register C Description

76543210

5VEN

PUREF

––––

GPU

Bit Name

Description

GPU

Global Power-Up Device (0 = Power Down; 1 = Power Up)

Reserved

Must Be Programmed to Zero (0)

Reserved

Must Be Programmed to Zero (0)

Reserved

Must Be Programmed to Zero (0)

Reserved

Must Be Programmed to Zero (0)

PUREF

REF Power (0 = Power Down; 1 = Power Up)

REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)

5VEN

Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

CONTROL REGISTER A

CONTROL REGISTER B

CONTROL REGISTER C

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