AD7376

–10–

REV. 0

The data setup and data hold times in the specification table

determine the data valid time requirements. The last seven bits

of the data word entered into the serial register are held when

CS returns high. At the same time CS goes high it transfers the

7-bit data to the VR latch.

SHDN

SDI

CLK

CK

D

Q

RS

CS

SERIAL

REGISTER

RS

SDO

Figure 42. Detail SDO Output Schematic of the AD7376

All digital inputs are protected with a series input resistor and

parallel Zener ESD structure shown in Figure 43. Applies to

digital input pins

CS, SDI, SDO, RS, SHDN, CLK

100

LOGIC

Figure 43. Equivalent ESD Protection Circuit

A,B,W

Figure 44. Equivalent ESD Protection Analog Pins