AD760

REV. A

–7–

CALIBRATED LINEARITY PERFORMANCE

The cumulative probability plots for the AD760 INL and DNL

shown in Figures 3 and 4 represent the maximum absolute-

value (peak) linearity error for each part. Roughly 100 parts

from each of 3 wafer lots were used.

The calibrated DNL and INL performance for the sample

populations shown also represent the expected performance for

a single part calibrated often. There is essentially no difference

between the expected performance of many parts calibrated

once and one part calibrated often. The AD760 calibrated per-

formance is guaranteed at any temperature within the operating

temperature range. The peak nonlinearity for the sample popu-

lations shown are also representative of the expected maximum

linearity errors of a single part recalibrated at temperature.

40

30

20

10

0

40

20

0

60

80

100

0

0.125

0.25

0.375

0.5

0.625

0.75

16-BIT LSB

Figure 3. AD760 Peak INL

40

30

20

10

0

40

20

0

60

80

100

0

0.125

0.25

0.375

0.5

16-BIT LSB

50

Figure 4. AD760 Peak DNL

ANALOG CIRCUIT CONNECTIONS

Internal scaling resistors provided in the AD760 may be con-

nected to produce a unipolar output range of 0 V to +10 V or a

bipolar output range of –10 V to +10 V. Gain and offset drift

are minimized in the AD760 because of the thermal tracking of

the scaling resistors with other device components.

UNIPOLAR CONFIGURATION

The configuration shown in Figure 5a will provide a unipolar

0 V to +10 V output range. In this mode a 50 resistor is tied

between REF OUT (Pin 26) and REF IN (Pin 25). It is pos-

sible to use the AD760 without any external components by

tying Pin 26 directly to Pin 25. Eliminating this resistor will

increase the gain error by 0.50% of FSR.

SPAN/BIP OFF

23

24

+10V REF

25

MAIN DAC

REFOUT

26

REFIN

50

Ω

10k

Ω

10k

Ω

9.95k

Ω

AD760

Figure 5a. 0 V to +10 V Unipolar Voltage Output

If it is desired to adjust the gain error to zero, this can be ac-

complished using the circuit shown in Figure 5b. The adjust-

ment procedure is as follows:

STEP 1 . . . OFFSET ADJUST

Initiate calibration sequence. CALOK (Pin 1) must remain high

throughout Gain Adjust.

STEP 2 . . . GAIN ADJUST

Turn all bits ON and adjust gain trimmer, R1, until the output

is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the

nominal full scale of 10.000000 volts.)

SPAN/BIP OFF

23

24

+10V REF

25

MAIN DAC

REFOUT

26

REFI N

R1

100

Ω

10k

Ω

10k

Ω

9.95k

Ω

AD760

Figure 5b. 0 V to +10 V Unipolar Voltage Output with

Gain Adjust

BIPOLAR CONFIGURATION

The circuit shown in Figure 6a will provide a bipolar output

voltage from –10.000000 V to +9.999694 V with positive full

scale occurring with all bits ON. As in the unipolar mode, resis-

tor R1 may be eliminated altogether to provide AD760 bipolar

operation without any external components. Eliminating this

resistor will increase the gain error by 0.50% of FSR in the

bipolar mode.