AD7677AST datasheet(15/20 Pages) AD

15 / 20 page

REV. 0

AD7677

–15–

analog input has to be settled when BUSY goes low. Also, at

power-up,

CNVST should be brought low once to initiate the

conversion process. In this mode, the AD7677 could sometimes

run slightly faster than the guaranteed limits in the impulse

mode of 666 kSPS. This feature does not exist in warp or

Normal modes.

CNVST

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

BUSY

Figure 11. Basic Conversion Timing

Although CNVST is a digital signal, it should be designed with

this special care with fast, clean edges and levels, with minimum

overshoot and undershoot or ringing.

For applications where the SNR is critical, the CNVST signal

should have a very low jitter. Some solutions to achieve that are to

use a dedicated oscillator for CNVST generation or, at least, to

clock it with a high frequency low jitter clock as shown in Figure 5.

RESET

DATA

BUSY

CNVST

Figure 12. RESET Timing

DIGITAL INTERFACE

The AD7677 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7677 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7677

to the host system interface digital supply. Finally, by using the

OB/

2C input pin, both two’s complement or straight binary

coding can be used.

The two signals,

CS and RD, control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually,

CS allows the selection of each AD7677 in

multicircuits applications and is held low in a single AD7677

design.

RD is generally used to enable the conversion result on

the data bus.

CNVST

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA

NEW DATA

t10

t11

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7677 is configured to use the parallel interface (Figure 13)

when the SER/

PAR is held low. The data eithercan be read

after each conversion, which is during the next acquisition phase,

or during the following conversion as shown, respectively, in

Figure 14 and Figure 15. When the data is read during the conver-

sion however, it is recommended that it is a read-only during

the first half of the conversion phase. This avoids any potential

feedthrough between voltage transients on the digital interface

and the most critical analog conversion circuitry.

DATA

BUS

t12

t13

BUSY

CURRENT

CONVERSION

Figure 14. Slave Parallel Data Timing for Reading (Read

After Convert)

CS = 0

CNVST,

CONVERSION

DATA

BUS

t12

t13

BUSY

Figure 15. Slave Parallel Data Timing for Reading (Read

During Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 16, the LSB byte is output on D[7:0] and

the MSB is output on D[15:8] when BYTESWAP is low. When

BYTESWAP is high, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16 bits of

data can be read in 2 bytes on either D[15:8] or D[7:0].

AD7677AST Datasheet(PDF) 15 Page - Analog Devices

AD7677AST Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL