AD7884AP datasheet(3/16 Pages) AD

3 / 16 page

AD7884/AD7885

REV. C

–3–

TIMING CHARACTERISTICS1, 2

Limit at +25 C

Limit at TMIN, TMAX

Parameter

(All Versions)

(A, B Versions)

Units

Conditions/Comments

ns min

CONVST

Pulse Width

100

ns max

CONVST

to BUSY Low Delay

ns min

to RD Setup Time

ns min

Pulse Width

ns min

to RD Hold Time

ns max

Data Access Time after RD

ns min

Bus Relinquish Time after RD

ns max

ns min

New Data Valid before Rising Edge of BUSY

ns min

HBEN to RD Setup Time

t10

ns min

HBEN to RD Hold Time

t11

ns min

HBEN Low Pulse Duration

t12

ns min

HBEN High Pulse Duration

t13

ns max

Propagation Delay from HBEN Falling to Data Valid

t14

ns max

Propagation Delay from HBEN Rising to Data Valid

NOTES

1Timing specifications in bold print are 100% production tested. All other times are sample tested at +5

°C to ensure compliance. All input signals are specified

with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-

olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true

bus relinquish time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

(VDD = +5 V

5%, VSS = –5 V

5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)

ORDERING GUIDE

Linearity

Temperature

Error

SNR

Package

Model

Range

(% FSR)

(dB)

Option

AD7884AN

–40

°C to +85°C

N-40A

AD7884BN

–40

°C to +85°C ±0.0075

N-40A

AD7884AP

–40

°C to +85°C

P-44A

AD7884BP

–40

°C to +85°C ±0.0075

P-44A

AD7885AN

–40

°C to +85°C

N-28A

AD7885BN

–40

°C to +85°C ±0.0075

N-28A

AD7885AAP –40

°C to +85°C

P-44A

AD7885ABP –40

°C to +85°C ±0.0075

P-44A

NOTES

1Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic

DIP (N) packages.

2N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).

TO OUTPUT PIN

+2.1V

I OL

C L

100pF

1.6mA

200

µA

Figure 1. Load Circuit for Access Time and Bus Relinquish

Time

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