REV. B

AD7887

–11–

MODES OF OPERATION

The AD7887 has a number of different modes of operation.

These are designed to provide flexible power management op-

tions. These options can be chosen to optimize the power dissi-

pation/throughput rate ratio for differing application requirements.

The modes of operation are controlled by the PM1 and PM0 bits

of the Control Register as previously outlined. For read-only

operation of the AD7887, the default mode of all 0s in the Con-

trol Register can be set up by tying the DIN line permanently

low.

Mode 1 (PM1 = 0, PM0 = 0)

This mode allows the user to control the powering down of the

part via the CS pin. Whenever CS is low, the AD7887 is fully

powered up; whenever CS is high, the AD7887 is in full shut-

down. When CS goes from high to low, all on-chip circuitry

starts to power up. It takes approximately, 5

µs for the AD7887

internal circuitry to be fully powered up. As a result, a conver-

sion (or sample-and-hold acquisition) should not be initiated

during this 5

µs.

Figure 13 shows a general diagram of the operation of the AD7887

in this mode. The input signal is sampled on the second rising

edge of SCLK following the CS falling edge. The user should

ensure that 5

µs elapses between the falling edge of CS and the

second rising edge of SCLK. In microcontroller applications,

this is readily achievable by driving the CS input from one of the

port lines and ensuring that the serial data read (from the micro-

controllers serial port) is not initiated for 5

µs. In DSP applica-

tions, where the CS is generally derived from the serial frame

synchronization line, it is usually not possible to separate the CS

falling edge and second SCLK rising edge by up to 5

µs without

affecting the speed of the rest of the serial clock. Therefore, the

user will need to write to the Control Register to exit this mode

and (by writing PM1 = 0 and PM0 = 1) put the part into Mode

2, i.e., normal mode. A second conversion will then need to be

initiated when the part is powered-up to get a conversion result.

The write operation which takes place in conjunction with this

second conversion can put the part back into Mode 1 and the

part will go into power-down mode when CS returns high.

Mode 2 (PM1 = 0, PM0 = 1)

In this mode of operation, the AD7887 remains fully powered

up regardless of the status of the CS line. It is intended for

fastest throughput rate performance as the user does not have to

worry about the 5

µs power-up time previously mentioned.

Figure 14 shows the general diagram of the operation of the

AD7887 in this mode.

The data presented to the AD7887 on the DIN line during the

first eight clock cycles of the data transfer are loaded to the

Control Register. To continue to operate in this mode, the user

must ensure that PM1 is loaded with 0 and PM0 is loaded with

1 on every data transfer.

The falling edge of CS initiates the sequence and the input

signal is sampled on the second rising edge of the SCLK input.

Sixteen serial clock cycles are required to complete the conver-

sion and access the conversion result. Once a data transfer is

complete (CS has returned high), another conversion can be

initiated immediately by bringing CS low again.

SCLK

CS

DOUT

DIN

1

16

CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.

PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE

4 LEADING ZEROS + CONVERSION RESULT

DATA IN

THE PART POWERS UP ON

CS

FALLING EDGE AS PM1 AND PM0 = 0

THE PART POWERS DOWN ON

CS

RISING EDGE AS PM1 AND PM0 = 0

Figure 13. Mode 1 Operation

SCLK

CS

DOUT

DIN

THE PART REMAINS POWERED UP

AT ALL TIMES AS

PM1 = 0 AND PM0 = 1

1

16

CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.

PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE

4 LEADING ZEROS + CONVERSION RESULT

DATA IN

Figure 14. Mode 2 Operation