REV. B

AD7887

–14–

MICROPROCESSOR INTERFACING

The serial interface on the AD7887 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7887 with some of the

more common microcontroller and DSP serial interface protocols.

AD7887 to TMS320C5x

The serial interface on the TMS320C5x uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the AD7887.

The CS input allows easy interfacing with an inverter between

the serial clock of the TMS320C5x and the AD7887 being the

only glue logic required. The serial port of the TMS320C5x is

set up to operate in burst mode with internal CLKX (TX serial

clock) and FSX (TX frame sync). The serial port control regis-

ter (SPC) must have the following setup: FO = 0, FSM = 1,

MCM = 1 and TXM = 1. The connection diagram is shown in

Figure 18.

AD7887*

DOUT

DIN

SCLK

CS

TMS320C5x*

*ADDITIONAL PINS OMITTED FOR CLARITY

CLKX

CLKR

DR

DT

FSX

FSR

Figure 18. Interfacing to the TMS320C5x

AD7887 to ADSP-21xx

The ADSP-21xx family of DSPs are easily interfaced to the

AD7887 with an inverter between the serial clock of the ADSP-

21xx and the AD7887. This is the only glue logic required. The

SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0

ITFS = 1

The connection diagram is shown in Figure 19. The ADSP-

21xx has the TFS and RFS of the SPORT tied together, with

TFS set as an output and RFS set as an input. The DSP oper-

ates in Alternate Framing Mode and the SPORT control regis-

ter is set up as described. The Frame synchronization signal

generated on the TFS is tied to CS and as with all signal pro-

cessing applications equidistant sampling is necessary. In this

example however, the timer interrupt is used to control the

sampling rate of the ADC and under certain conditions, equi-

distant sampling may not be achieved.

The Timer registers etc., are loaded with a value that will pro-

vide an interrupt at the required sample interval. When an inter-

rupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and hence

the reading of data. The frequency of the serial clock is set in

the SCLKDIV register. When the instruction to transmit with

TFS is given (i.e., AX0 = TX0), the state of the SCLK is

checked. The DSP will wait until the SCLK has gone High,

Low and High before transmission will start. If the timer and

SCLK values are chosen such that the instruction to transmit

occurs on or near the rising edge of SCLK, the data may be

transmitted or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3

then a SCLK of 2 MHz is obtained, and 8 master clock periods

will elapse for every 1 SCLK period. If the timer registers are

loaded with the value 803, then 100.5 SCLKs will occur be-

tween interrupts and subsequently between transmit instruc-

tions. This situation will result in nonequidistant sampling as

the transmit instruction is occurring on an SCLK edge. If the

number of SCLKs between interrupts is a whole integer number

of N, equidistant sampling will be implemented by the DSP.

AD7887*

DOUT

DIN

SCLK

CS

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

DR

DT

RFS

TFS

ADSP-21xx*

Figure 19. Interfacing to the ADSP-21xx

AD7887 to DSP56xxx

The connection diagram in Figure 20 shows how the AD7887

can be connected to the SSI (Synchronous Serial Interface) of

the DSP56xxx family of DSPs from Motorola. The SSI is oper-

ated in Synchronous Mode (SYN bit in CRB = 1) with inter-

nally generated 1-bit clock period frame sync for both TX and

RX (Bits FSL1 =1 and FSL0 =0 in CRB). Set the word length

to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An inverter

is also necessary between the SCLK from the DSP56xxx and

the SCLK pin of the AD7887 as shown in Figure 20.

DOUT

DIN

SCLK

CS

*ADDITIONAL PINS OMITTED FOR CLARITY

DSP56xxx*

AD7887*

SCK

SRD

STD

SC2

Figure 20. Interfacing to the DSP56xxx