AD7898

–14–

REV. 0

To chip-select the AD7898 in systems where more than one

device is connected to the 8x51/L51’s serial port, a port bit

configured as an output, from one of the 8x51/L51’s parallel

ports can be used to gate on or off the serial clock to the AD7898.

A simple AND function on this port bit and the serial clock from

the 8x51/L51 will provide this function. The port bit should be

high to select the AD7898 and low when it is not selected.

The AD7898 outputs the MSB first during a read operation,

while the 8xL51 expects the LSB first. Therefore, the data which

is read into the serial buffer needs to be rearranged before the

correct data format from the AD7898 appears in the accumulator.

The serial clock rate from the 8x51/L51 is limited to signifi-

cantly less than the allowable input serial clock frequency with

which the AD7898 can operate. As a result, the time to read

data from the part will actually be longer than the conversion

time of the part. This means that the AD7898 cannot run at its

maximum throughput rate when used with the 8x51/L51.

68HC11/L11 to AD7898 Interface

An interface circuit between the AD7898 and the 68HC11/L11

microcontroller is shown in Figure 14. For the interface shown,

the 68L11 SPI port is used, and the 68L11 is configured in its

single-chip mode. The 68L11 is configured in the master mode

with its CPOL bit set to a logic zero and its CPHA bit set to a

logic one. As with the previous interface, the diagram shows the

simplest form of the interface where the AD7898 is the only part

connected to the serial port of the 68L11 and, therefore, no

decoding of the serial read operations is required.

AD7898

SDATA

MISO

SCLK

SCK

68HC11/L11

Figure 14. 68HC11/L11 to AD7898 Interface

Once again, to chip-select the AD7898 in systems where more

than one device is connected to the 68HC11’s serial port, a port

bit configured as an output from one of the 68HC11’s parallel

ports can be used to gate on or off the serial clock to the AD7898.

A simple AND function on this port bit and the serial clock

from the 68L11 will provide this function. The port bit should

be high to select the AD7898 and low when it is not selected.

The serial clock rate from the 68HC11/L11 is limited to signifi-

cantly less than the allowable input serial clock frequency with

which the AD7898 can operate. As a result, the time to read

data from the part will actually be longer than the conversion

time of the part. This means that the AD7898 cannot run at its

maximum throughput rate when used with the 68HC11/L11.

ADSP-2103/ADSP-2105 to AD7898 Interface

An interface circuit between the AD7898 and the ADSP-2103/

ADSP-2105 DSP processor is shown in Figure 15. In the inter-

face shown, the RFS1 output from the ADSP-2103/ADSP-2105’s

SPORT1 serial port is used to gate the serial clock (SCLK1) of

the ADSP-2103/ADSP-2105 before it is applied to the SCLK

input of the AD7898. The RFS1 output is configured for active

high operation. The interface ensures a noncontinuous clock for

the AD7898’s serial clock input with only 16 serial clock pulses

provided and the serial clock line of the AD7898 remaining low

between data transfers. A read operation should be timed to

occur 3.3

µs after CONVST goes low. The SDATA line from

the AD7898 is connected to the DR1 line of the ADSP-2103/

ADSP-2105’s serial port.

AD7898

SCLK

SCLK1

RFS1

ADSP-2103/

ADSP-2105

SDATA

DR1

Figure 15. ADSP-2103/ADSP-2105 to AD7898 Interface

The timing relationship between the SCLK1 and RFS1 outputs

of the ADSP-2103/ADSP-2105 are such that the delay between

the rising edge of the SCLK1 and the rising edge of an active

high RFS1 is up to 30 ns. There is also a requirement that data

must be set up 10 ns prior to the falling edge of the SCLK1 to

be read correctly by the ADSP-2103/ADSP-2105. The data

SCLK input. Assuming a 10 ns propagation delay through the

external AND gate, the high time of the SCLK1 output of the

ADSP-2105 must be

≥ (30 + 60 +10 +10) ns, i.e., ≥ 110 ns.

This means that the serial clock frequency with which the inter-

face of Figure 15 can work is limited to 4.5 MHz. However,

there is an alternative method that allows for the ADSP-2105

SCLK1 to run at 5 MHz (the max serial clock frequency of the

SCLK1 output). The arrangement occurs when the first leading

zero of the data stream from the AD7898 cannot be guaranteed

to be clocked into the ADSP-2105 due to the combined delay of

the RFS signal and the data access time of the AD7898. In most

cases, this is acceptable because there will still be three leading

zeros followed by the 12 data bits.

Another alternative scheme is to configure the ADSP-2103/

ADSP-2105 so that it accepts an external noncontinuous serial

clock. In this case, an external noncontinuous serial clock is

provided that drives the serial clock inputs of both the ADSP-

2103/ADSP-2105 and the AD7898. In this scheme, the serial

clock frequency is limited to 15 MHz by the AD7898.

DSP56002/L002 to AD7898 Interface

Figure 16 shows an interface circuit between the AD7898 and

the DSP56002/L002 DSP processor. The DSP56002/L002 is

configured for normal mode asynchronous operation with gated

clock. It is also set up for a 16-bit word with SCK as gated clock

output. In this mode, the DSP56002/L002 provides sixteen

serial clock pulses to the AD7898 in a serial read operation.

Because the DSP56002/L002 assumes valid data on the first

falling edge of SCK, the interface is simply 2-wire as shown in

Figure 16.

AD7898

SCLK

SCK

DSP56002/L002

SDATA

SDR

Figure 16. DSP56002/L002 to AD7898 Interface

MICROPROCESSOR INTERFACING FOR MODE 1

The serial interface on the AD7898 for Mode 1 allows the parts

to be directly connected to a range of many different micropro-

cessors. This section explains how to interface the AD7898 with

some of the more common microcontroller and DSP serial

interface protocols for Mode 1 operation.