AD7937

–4–

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Description

1

AGNDA

Analog Ground for DAC A.

Current output terminal of DAC A.

Feedback resistor for DAC A.

Reference input to DAC A.

5

CS

Chip Select Input Active low.

6–11

DB0–DB7

Eight data inputs, DB0–DB7.

13, 14

12

DGND

Digital Ground.

15

A0

Address Line 0.

16

A1

Address Line 1.

17

CLR

Clear Input. Active low. Clears all

registers.

18

WR

Write Input. Active low.

19

UPD

Updates DAC Registers from inputs

registers.

20

Power supply input. Nominally 5 V to

15 V, with

±10% tolerance.

21

Reference input to DAC B.

22

Feedback resistor for DAC B.

23

Current output terminal of DAC B.

24

AGNDB

Analog Ground for DAC B.

PIN CONFIGURATION

SOIC

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

AD7937

DGND

DB5

DB4

DB3

DB2

AGNDA

DB1

DB0

CS

DB6

DB7

A0

A1

CLR

AGNDB

WR

UPD

CIRCUIT INFORMATION – D/A SECTION

The AD7937 contains two identical 12-bit multiplying D/A

converters. Each DAC consists of a highly stable R-2R ladder

and 12 N-channel current steering switches. Figure 2 shows a

simplified D/A circuit for DAC A. In the R-2R ladder, binary

current flowing in each ladder leg is constant, irrespective of

a voltage output.

AGNDA

R

R

2R

S11

2R

S10

2R

S0

2R

R

Figure 2. Simplified Circuit Diagram for DAC A

EQUIVALENT CIRCUIT ANALYSIS

Figure 3 shows the equivalent circuit for one of the D/A con-

verters (DAC A) in the AD7937. A similar equivalent circuit

can be drawn for DAC B.

AGNDA

R

R

R

Figure 3. Equivalent Analog Circuit for DAC A

and varies from about 50 pF to 100 pF with digital input code.

leakages and approximately doubles every 10

°C. R

lent output resistance of the device which varies with input code.

DIGITAL CIRCUIT INFORMATION

The digital inputs are designed to be both TTL and 5 V CMOS

compatible. All logic inputs are static protected MOS gates with

typical input currents of less than 1 nA.

Table I. AD7937 Truth Table

CLR UPD CS WR A1 A0 Function

1

1

1

X

X

X

No Data Transfer

1

1

X

1

X

X

No Data Transfer

0

X

X

X

X

X

All Registers Cleared

1

1

0

0

0

0

DAC A LS Input Register

Loaded with DB7–DB0 (LSB)

1

1

0

0

0

1

DAC A MS Input Register

Loaded with DB3 (MSB)–DB0

1

1

0

0

1

0

DAC B LS Input Register

Loaded with DB7–DB0 (LSB)

1

1

0

0

1

1

DAC B MS Input Register

Loaded with DB3 (MSB)–DB0

1

0

1

0

X

X

DAC A, DAC B Registers

Updated Simultaneously from

Input Registers

1

0

0

0

X

X

DAC A, DAC B Registers are

Transparent

NOTE: X = Don’t care