AD8017

–15–

REV. A

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8017 requires

careful attention to board layout and component selection.

Table II shows recommended component values for the AD8017

and Figures 42–44 show recommended layouts for the 8-lead

SOIC package for a positive gain. Proper RF design techniques

and low parasitic component selections are mandatory.

Table II. Typical Bandwidth vs. Gain Setting Resistors

)

Small Signal

Gain

–3 dB BW (MHz)

–1

619

619

54.5

110

+1

619

49.9

320

+2

619

619

49.9

160

+10

619

68.8

49.9

40

Ω characteristic input impedance.

The PCB should have a ground plane covering all unused

portions of the component side of the board to provide a low

impedance ground path. The ground plane should be removed

from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Fig-

ures 4 and 7). One end should be connected to the ground

plane and the other within 1/8 in. of each power pin. An addi-

tional (4.7

µF–10 µF) tantalum electrolytic capacitor should be

connected in parallel.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to

a minimum. Capacitance greater than 1.5 pF at the inverting

input will significantly affect high speed performance when

operating at low noninverting gain.

Figure 42. Universal SOIC Noninverter Top Silkscreen

Figure 43. Universal SOIC Noninverter Top

Figure 44. Universal SOIC Noninverter Bottom