AD8108AST datasheet(6/28 Pages) AD

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AD8108/AD8109

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Table III. Operation Truth Table

SER/

UPDATE

CLK

DATA IN

DATA OUT

RESET

PAR

Operation/Comment

No change in logic.

Data i

Data i-32

The data on the serial DATA IN line is loaded

into serial register. The first bit clocked into

the serial register appears at DATA OUT 32

clocks later.

D0 . . . D3,

NA in Parallel

The data on the parallel data lines, D0–D3, are

A0 ...A2

Mode

loaded into the 32-bit serial shift register loca-

tion addressed by A0–A2.

Data in the 32-bit shift register transfers into the

parallel latches that control the switch array.

Latches are transparent.

Asynchronous operation. All outputs are disabled.

Remainder of logic is unchanged.

CLK

UPDATE

OUT0

CLR

DATA IN

(SERIAL)

(OUTPUT ENABLE)

SER/PAR

RESET

(OUTPUT ENABLE)

OUT0 EN

DATA

OUT

PARALLEL DATA

CLK

D Q

CLK

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

OUT5 EN

OUT6 EN

OUT7 EN

OUT0

OUT1

OUT6

CLR

OUT7

CLR

DECODE

OUTPUT ENABLE

SWITCH MATRIX

Figure 4. Logic Diagram

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