| Electronic Components Datasheet Search |
|
MMA9550LT Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MMA9550LT Datasheet(HTML) 20 Page - Freescale Semiconductor, Inc |
|
20 / 25 page ![]() MMA955xL Sensors 20 Freescale Semiconductor, Inc. 4.12 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 5 on page 17. Unless otherwise specified, propagation delays are measured from the 50-percent to 50-percent point. Rise and fall times are measured between the 10-percent and 90-percent points, as shown in the following figure. Figure 10. Input signal measurement references The subsequent figure shows the definitions of the following signal states: • Active state, when a bus or signal is driven and enters a low-impedance state • Three-stated, when a bus or signal is placed in a high-impedance state • Data Valid state, when a signal level has reached VOL or VOH • Data Invalid state, when a signal level is in transition between VOL and VOH Figure 11. Signal states 4.13 General Timing Control Table 12. General timing characteristics(1) 1. All conditions at nominal supply: VDD = VDDA = 1.8 V Characteristic Symbol Condition(s) Min Typ Max Unit VDD rise time Trvdd 10% to 90% 1 ms POR release delay(2) 2. This is the time measured from VDD = VPOR until the internal reset signal is released. TPOR Power-up 0.35 1.5 ms Warm-up time TWU From STOPNC 7 sample periods Frequency of operation FOPH Full Speed Clock 8 MHz FOPL Slow Clock 62.5 KHz System clock period tCYCH Full Speed Clock 125 ns tCYCL Slow Clock 16 μs Full/Slow clock ratio 128 Oscillator frequency absolute accuracy @ 25°C Full Speed Clock -5 +5 % Oscillator frequency variation over temperature (-40°C to 85°C vs. ambient) Slow Clock -6 +6 % Minimum RESET assertion duration tRA 4T(3) 3. In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 μs. VIH VIL Fall Time Input Signal Note: The midpoint is VIL + (VIH – VIL)/2. Midpoint1 Low High 90% 50% 10% Rise Time Data Invalid State Data1 Data 3-stated Data3 Valid Data2 Data3 Data1 Valid Data Active Data Active Data1 Valid |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |