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AD9500

–4–

REV. D

PIN FUNCTION DESCRIPTIONS

Pin Name

Description

D4–D6

One of eight digital inputs used to set the programmed delay.

D7 (MSB)

One of eight digital inputs used to set the programmed delay. D7 (MSB) is the most significant bit of the

digital input word.

ECLREF

ECL midpoint reference, nominally –1.3 V. Use of the ECL REF allows either of the TRIGGER or RESET

inputs to be configured for single-ended ECL inputs.

OFFSET ADJUST

The OFFSET ADJUST is used to adjust the minimum propagation delay (tPD), by pulling or pushing a

small current out of or into the pin.

CS allows the full-scale range to be extended by using an external timing capacitor. The value of CEXT,

connected between CS and +VS, may range from no external capacitance to 0.1

µF+.

See RS (CINTERNAL = 10 pF).

+VS

Positive supply terminal, nominally +5.0 V.

TRIGGER

Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by

the programmed delay, after the triggering event. The programmed delay is set by the digital input word.

The TRIGGER input must be driven in conjunction with the

TRIGGER input.

TRIGGER

Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the

programmed delay, after the triggering event. The programmed delay is set by the digital input word. The

TRIGGER input must be driven in conjunction with the TRIGGER input.

RESET

Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal

is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be

equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the

RESET input.

RESET

Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a

signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will

be equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the

RESET input.

One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on

the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output.

One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on

the

Q output. A “resetting” event at the inputs will produce a logic HIGH on the Q output.

output is parallel to the

Q output. The Q

output is typically used to drive delaying circuits for extend-

ing output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the Q

output. A

“resetting” event at the inputs will produce a logic HIGH on the Q

output.

ECL COMMON

The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but nor-

mally it is tied to the circuit ground for standard ECL outputs.

–VS

Negative supply terminal, nominally –5.2 V.

RS is the reference current setting terminal. An external setting resistor, RSET, connected between RS and

–VS determines the internal reference current. See CS (250 Ω ≤ RSET ≤ 50 kΩ).

GROUND

The ground return for the TTL and analog inputs.

LATCH ENABLE

Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the

logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously

updated through the logic inputs D0 thru D7.

D0 (LSB)

One of eight digital inputs used to set the programmed delay. D0 (LSB) is the least significant bit of the

digital input word.

D3–D1

One of eight digital inputs used to set the programmed delay.

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