AD977/AD977A

–12–

REV. D

For both the AD977 and the AD977A the data should be

clocked out during the first half of

BUSY so not to degrade

conversion performance. For the AD977 this requires use of a

4.8 MHz DATACLK or greater, with data being read out as

soon as the conversion process begins. For the AD977A it

requires use of a 10 MHz DATACLK or greater.

It is not recommended that data be shifted through the TAG

input in this mode as it will certainly result in clocking of data

during the second half of the conversion.

EXTERNAL CONTINUOUS CLOCK DATA READ AFTER

CONVERSION WITH SYNC OUTPUT GENERATED

Figure 8 illustrates the method by which data from conversion

“n” can be read after the conversion is complete using a con-

tinuous external clock, with the generation of a SYNC output.

What permits the generation of a SYNC output is a transition of

DATACLK while either

CS is high or while both CS and R/C are

low.

With a continuous clock the

CS pin cannot be tied low as it

could be with a discontinuous clock. Use of a continuous clock,

while a conversion is occurring, can increase the DNL and

Transition Noise of the AD977/AD977A.

After a conversion is complete, indicated by

BUSY returning

high, the result of that conversion can be read while

CS is low

and R/

C is high. In Figure 8 clock pulse #0 is used to enable the

generation of a SYNC pulse. The SYNC pulse is actually clocked

out approximately 40 ns after the rising edge of clock pulse #1.

The SYNC pulse will be valid on the falling edge of clock pulse

#1 and the rising edge of clock pulse #2. The MSB will be valid

on the falling edge of clock pulse #2 and the rising edge of clock

pulse #3. The LSB will be valid on the falling edge of clock

pulse #17 and the rising edge of clock pulse #18. Approximately

50 ns after the rising edge of clock pulse #18 the DATA output

pin will reflect the state of the TAG input pin during the rising

edge of clock pulse #2.

When reading data after the conversion is complete, with the

highest frequency permitted for DATACLK (15.15 MHz) and,

with the AD977A, the maximum possible throughput is approxi-

mately 195 kHz and not the rated 200 kHz.

For details on use of the TAG input with this mode see the Use

of the TAG Input section.

Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/

INT Set to Logic High)

CS

BUSY

R/C

BIT 15

(MSB)

BIT 14

TAG 2

BIT 0

(LSB)

TAG 0

TAG 1

TAG 0

TAG 1

TAG 2

TAG 16

TAG 17

TAG 18

TAG 19

0

1

2

3

4

17

18

EXT

DATACLK

TAG

DATA

SYNC