AD977 datasheet(19/24 Pages) AD

19 / 24 page

AD977/AD977A

–19–

REV. D

OFFSET AND GAIN ADJUSTMENT

The AD977/AD977A is factory trimmed to minimize gain,

offset and linearity errors. In some applications, where the ana-

log input signal is required to meet the full dynamic range of the

ADC, the gain and offset errors need to be externally trimmed

to zero. Figures 12 and 13 show the required trim circuitry to

correct for these offset and gain errors.

Where adjustment is required, offset error must be corrected

before gain error. To achieve this in the bipolar input configura-

tion, trim the offset potentiometer with the input voltage set to

1/2 LSB below ground. Then adjust the potentiometer until the

major carry transition is located between 1111 1111 1111 1111

and 0000 0000 0000 0000. To adjust the gain error, an analog

signal should be input at either the first code transition (ADC

negative full scale) or the last code transition (ADC positive full

scale). Thus, to adjust for full-scale error, an input voltage of

FS/2 – 3/2 LSBs can be applied to VIN, and the gain potentiom-

eter should be adjusted until the output code flickers between

the last positive code transition 0111 1111 1111 1111 and 0111

1111 1111 1110. Should the first code transition need adjust-

ing, the trim procedure should consist of applying an analog

input signal of –FS/2 + 1/2 LSB to the VIN input and adjust-

ing the trim until the output code flickers between 1000 0000

0000 0000 and 1000 0000 0000 0001.

AC PERFORMANCE

The AD977/AD977A is fully specified and tested for dynamic

performance specifications. The ac parameters are required for

signal processing applications such as speech recognition and

spectrum analysis. These applications require information on

the ADC’s effect on the spectral content of the input signal.

Hence, the parameters for which the AD977/AD977A is specified

include S/(N+D), THD and Spurious Free Dynamic Range.

These terms are discussed in greater detail in the following

sections.

As a general rule, it is recommended that the results from sev-

eral conversions be averaged to reduce the effects of noise and

thus improve parameters such as S/(N+D) and THD. The ac

performance of the AD977/AD977A can be optimized by operat-

ing the ADC at its maximum sampling rate of 100 kHz/200 kHz

and digitally filtering the resulting bit stream to the desired signal

bandwidth. By distributing noise over a wider frequency range

the noise density in the frequency band of interest can be

reduced. For example, if the required input bandwidth is 50 kHz,

FREQUENCY – kHz

–10

100

–40

–70

–130

–20

–30

–60

–50

–90

–120

–80

–110

–100

90 95

253545

7585

5280 POINT FFT

FSAMPLE = 200kHz

FIN = 20kHz, 0dB

SNRD = 86dB

THD = –101dB

Figure 17. FFT Plot

the AD977/AD977A could be oversampled by a factor of 2/4.

This would yield a 3/6 dB improvement in the effective SNR

performance.

DC PERFORMANCE

The factory calibration scheme used for the AD977/AD977A

compensates for bit weight errors that may exist in the capacitor

array. The mismatch in capacitor values is adjusted (using the

calibration coefficients) during a conversion resulting in excel-

lent dc linearity performance. Figures 18, 19, 20, 21, 22 and 23,

respectively, show typical INL, typical DNL, typical positive and

negative INL and DNL distribution plots for the AD977/AD977A

at 25

°C.

A histogram test is a statistical method for deriving an A/D

converter’s differential nonlinearity. A ramp input is sampled by

the ADC and a large number of conversions are taken at each

voltage level, averaged then stored. The effect of averaging is to

reduce the transition noise by 1/n. If 64 samples are averaged at

each point, the effect of transition noise is reduced by a factor of

8, i.e., a transition noise of 0.8 LSBs rms is reduced to

0.1 LSBs rms. Theoretically the codes, during a test of DNL,

would all be the same size and therefore have an equal number

of occurrences. A code with an average number of occurrences

would have a DNL of “0.” A code that is different from the

average would have a DNL that was either greater or less than

zero LSB. A DNL of –1 LSB indicates that there is a missing

code present at the 16-bit level and that the ADC exhibits 15-

bit performance.

OUTPUT CODE – K

066

1015

2025

3035

2.0

–2.0

–0.5

–1.0

–1.5

1.0

0.5

1.5

100%

Figure 18. INL Plot

OUTPUT CODE – K

066

1015

2025

3035

2.0

–2.0

–0.5

–1.0

–1.5

1.0

0.5

1.5

100%

Figure 19. DNL Plot

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