AD9802

–4–

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin #

Pin Name

Type

Description

1

ADVSS

P

Analog Ground

2–11

D0–D9

DO

Digital Data Outputs: D0 = LSB, D9 = MSB

12

DRVDD

P

+3 V Digital Driver Supply

13

DRVSS

P

Digital Driver Ground

14

DSUBST

P

Digital Substrate

15

DVSS

P

Digital Ground

16

ADCCLK

DI

ADC Sample Clock Input

17

DVDD

P

+3 V Digital Supply

18

STBY

DI

Power-Down (Active High)

19

PBLK

DI

Pixel Blanking (Active Low)

20

CLPOB

DI

Black Level Restore Clamp (Active Low)

21

SHP

DI

Reference Sample Clock Input

22

SHD

DI

Data Sample Clock Input

23

CLPDM

DI

Input Clamp (Active Low)

24

DVSS

P

Digital Ground

25

CCDBYP2

AO

CCD Bypass. Decouple to analog ground through 0.1

µF.

26

DIN

AI

CDS Input. Tie to Pin 27 and AC-Couple to CCD output through 0.1

µF.

27

PIN

AI

CDS Input. See above.

28

CCDBYP1

AO

CCD Bypass. Decouple to analog ground through 0.1

µF.

29

PGACONT1

AI

Coarse PGA Gain Control (0.3 V–2.7 V). Decoupled to analog ground through 0.1

µF.

30

PGACONT2

AI

Fine PGA Gain Control

31

ACVSS

P

Analog Ground

32

CLAMP_BIAS

AO

Clamp Bias Level. Decouple to analog ground through 0.1

µF.

33

ACVDD

P

+3 V Analog Supply

34, 35

TEST1, TEST2

AI

Reserved Test Pins. Should be left NC or pulled high to ACVDD.

36

ADCIN

AI

Direct ADC Analog Input (See Driving the Direct ADC Input)

37

CMLEVEL

AO

Common-Mode Level. Decouple to analog ground through 0.1

µF.

38

SHABYP

AO

Internal Bias Level. Decouple to analog ground through 0.1

µF.

39

MODE2

DI

ADC Test Mode Control (See Digital Output Data Control.)

40

MODE1

DI

ADC Test Mode Control (See Digital Output Data Control.)

41

ADCMODE

DI

ADC Input Control. Logic low for CDS/PGA, high for direct input.

42

NC

No Connect

43

ADVDD

P

+3 V Analog Supply

44, 45

ADVSS

P

Analog Ground

46

SUBST

P

Substrate. Connect to analog ground.

47

VRB

AO

Bottom Reference Bypass. Decouple to analog ground through 0.1

µF.

48

VRT

AO

Top Reference Bypass

NOTE

Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

PIN CONFIGURATION

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

ADVSS

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D9

DRVDD

NC = NO CONNECT

AD9802

ADCIN

TEST2

TEST1

ACVDD

CLAMP_BIAS

ACVSS

PGACONT2

PGACONT1

CCDBYP1

PIN

DIN

CCDBYP2