AD9803JST datasheet(16/19 Pages) AD

16 / 19 page

AD9803

–16–

REV. 0

NOTE: With the exception of a write to the PGA register dur-

ing AUX-mode, all data writes must be 10 bits. During an

AUX-mode write to the PGA register, only 8 bits of data are

required. If more than 14 SCK rising edges are applied during a

write operation, additional SCK pulses will be ignored (see

Figure 35). All reads must be 10 bits to receive valid register

contents. All registers default to 0s on power-up, except for the

A-register which defaults to 11. Thus, on power-up, the AD9803

defaults to CCD mode. During the power-up phase, it is recom-

mended that SL be HIGH and SCK be LOW to prevent acci-

dental register write operations. SDATA may be unknown. The

RNW bit (“Read/Not Write”) must be LOW for all write opera-

tions to the serial interface, and HIGH when reading back from

the serial interface registers.

APPLICATIONS INFORMATION

Power and Grounding Recommendations

The AD9803 should be treated as an analog component when

used in a system. The same power supply and ground plane

should be used for all of the pins. In a two-ground system, this

requires that the digital supply pins be decoupled to the analog

ground plane and the digital ground pins be connected to ana-

log ground for best noise performance. Separate digital supplies

can be used, particularly if slightly different driver supplies are

needed, but the digital power pins should still be decoupled to

the same point as the digital ground pins (the analog ground

plane). If the AD9803 digital outputs need to drive a bus or

substantial load, then a buffer should be used at the AD9803’s

outputs, with the buffer referenced to system digital ground. In

some cases, when system digital noise is not substantial, it is

acceptable to split the ground pins on the AD9803 to separate

analog and digital ground planes. If this is done, be sure to

connect the two ground planes together at the AD9803.

To further improve performance, isolating the driver supply

DRVDD from DVDD with a ferrite bead can help reduce kick-

back effects during major code transitions. Alternatively, the

use of damping resistors on the digital outputs will reduce the

output rise times, also reducing the kickback effect.

Application Circuit Utilizing the AD9803’s Digital Gain Control

Figure 37 shows the recommended circuit configuration for

CCD-Mode operation when using the 3-wire serial interface.

The analog PGA control pins, PGACONT1 and PGACONT2,

should be shorted together and decoupled to ground. If the two

auxiliary DACs are not used, then Pins 39 and 40 (DAC1 and

DAC2) may be grounded.

Using the AD9803 in AD9801 Sockets

The AD9803 may be easily used in existing AD9801 designs

without any circuit modifications. Most of the pin assignments

are the same for both ICs. Table I outlines the differences. The

circuit of Figure 38 shows the necessary connections for the

AD9803 when used in an existing AD9801 socket. The power-

on reset in the AD9803 assures that the device will power-up in

CCD-mode, with analog PGA gain control.

Table I. AD9801/AD9803 Pin Differences

No.

AD9801

AD9803

AD9801 Connection

ADVSS

Ground

DSUBST

DVSS

Ground

DVSS

ACLP

Ground

DVSS

Ground

CLAMP_BIAS

CLPBYP

Decoupled with 0.1

µF

to Ground

ACVDD

AUXIN

+3 Volt Supply

ACVDD

AUXCONT

+3 Volt Supply

INT_BIAS1

ADCIN

Decoupled with 0.1

µF

to Ground

INT_BIAS2

VTRBYP

Decoupled with 0.1

µF

to Ground

MODE2

DAC1

Ground

MODE1

DAC2

Ground

ADVSS

Ground

ADVDD

SCK

+3 Volt Supply

ADVSS

SDATA

Ground

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