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AD9850 Datasheet(PDF) 8 Page - Analog Devices |
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AD9850 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 19 page ![]() AD9850 –8– REV. E +VS DATA BUS LOW-PASS FILTER GND PROCESSOR XTAL OSC CLK IOUTB VINN VINP QOUT QOUTB IOUT 100k 100k 200 100 470pF 200 COMP TRUE CMOS CLOCK OUTPUTS RSET AD9850 5-POLE ELLIPTICAL 42MHz LOW-PASS 200 IMPEDANCE 8-b 5 PARALLEL DATA, OR 1-b 40 SERIAL DATA, RESET, AND 2 CLOCK LINES Figure 13. Basic AD9850 Clock Generator Application with Low-Pass Filter VCA Rx IF IN ADC ENCODE I/Q MIXER AND LOW-PASS FILTER I Q 8 8 AD9059 DUAL 8-BIT ADC DIGITAL DEMODULATOR Rx BASEBAND DIGITAL DATA OUT ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL PN RATE AD9850 CLOCK GENERATOR 32 CHIP/SYMBOL/PN RATE DATA 125MHz REFERENCE CLOCK AGC Figure 14. AD9850 Clock Generator Application in a Spread-Spectrum Receiver IF FREQUENCY IN TUNING WORD AD9850 COMPLETE-DDS 125MHz REFERENCE FILTER RF FREQUENCY OUT FILTER a. Frequency/Phase–Agile Local Oscillator TUNING WORD AD9850 COMPLETE- DDS 125MHz REFERENCE CLOCK FILTER RF FREQUENCY OUT PHASE COMPARATOR LOOP FILTER VCO DIVIDE-BY-N b. Frequency/Phase–Agile Reference for PLL TUNING WORD REF FREQUENCY RF FREQUENCY OUT PHASE COMPARATOR LOOP FILTER VCO FILTER PROGRAMMABLE “DIVIDE-BY-N” FUNCTION AD9850 COMPLETE- DDS c. Digitally-Programmable ”Divide-by-N“ Function in PLL Figure 15. AD9850 Complete-DDS Synthesizer in Frequency Up-Conversion Applications THEORY OF OPERATION AND APPLICATION The AD9850 uses direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/phase-agile sine wave. The digital sine wave is con- verted to analog form via an internal 10-bit high speed D/A converter, and an onboard high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS- compatible output square wave. DDS technology is an innova- tive circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz with a 125 MHz reference clock ap- plied. The AD9850’s output waveform is phase-continuous when changed. The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 16. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2 N number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. When the counter overflows it wraps around, making the phase accumulator’s output contiguous. The frequency tuning word sets the modulus of the counter that effectively determines the size of the increment ( ∆ Phase) that gets added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the ac- cumulator overflows, which results in a higher output fre- quency. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula: fOUT = ( ∆ Phase × CLKIN)/232 where: ∆ Phase = value of 32-bit tuning word CLKIN = input reference clock frequency in MHz fOUT = frequency of the output signal in MHz The digital sine wave output of the DDS block drives the inter- nal high speed 10-bit D/A converter that reconstructs the sine |
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