AD9850 datasheet(11/19 Pages) AD

Part #	AD9850

Description	CMOS, 125 MHz Complete DDS Synthesizer

PDF	19 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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11 / 19 page

AD9850

–11–

REV. E

tRH

tRL

tRR

tRS

tOL

COS (0)

REF CLK

COS OUT

RESET

tRH

CLK DELAY AFTER RESET RISING EDGE

3.5ns

tRL

RESET FALLING EDGE AFTER CLK

3.5ns

tRR

RECOVERY FROM RESET

2 CLK CYCLES

tRS

MINIMUM RESET WIDTH

5 CLK CYCLES

tOL

RESET OUTPUT LATENCY

13 CLK CYCLES

SYMBOL

DEFINITION

MIN SPEC

RESULTS OF RESET:

– FREQUENCY/PHASE REGISTER SET TO 0

– ADDRESS POINTER RESET TO W0

– POWER-DOWN BIT RESET TO “0”

– DATA INPUT REGISTER UNEFFECTED

Figure 19. Master Reset Timing Sequence

XXXXX100

DATA (W0)

W CLK

FQ UD

REF CLK

INTERNAL CLOCKS DISABLED

DAC STROBE

Figure 20. Parallel-Load Power-Down Sequence/Internal Operation

XXXXX000

DATA (W0)

W CLK

FQ UD

REF CLK

INTERNAL CLOCKS ENABLED

Figure 21. Parallel-Load Power-Up Sequence/Internal Operation

AD9850 Datasheet(PDF) 11 Page - Analog Devices

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