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STM32F407IG Datasheet(PDF) 109 Page - STMicroelectronics

Part # STM32F407IG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  180 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IG Datasheet(HTML) 109 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 3
109/180
5.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 46).
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 13.
Figure 36.
Recommended NRST pin protection
1.
The reset network protects the device against parasitic resets.
2.
The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 49. Otherwise the reset is not taken into account by the device.
Table 49.
NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
(1)
1.
Guaranteed by design, not tested in production.
NRST Input low level voltage
–0.5
-
0.8
V
VIH(NRST)
(1)
NRST Input high level voltage
2
-
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
RPU
Weak pull-up equivalent resistor(2)
2.
The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum
(~10% order)
.
VIN = VSS
30
40
50
k
Ω
VF(NRST)
(1)
NRST Input filtered pulse
-
-
100
ns
VNF(NRST)
(1)
NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal
Reset source
20
-
-
µs



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