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STM32F407IG Datasheet(PDF) 151 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 151 Page - STMicroelectronics |
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151 / 180 page ![]() STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 3 151/180 Figure 72. SD default mode 5.3.28 RTC characteristics Table 86. SD / MMC characteristics(1) 1. TBD stands for “to be defined”. Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF TBD TBD MHz - SDIO_CK/fPCLK2 frequency ratio - - TBD - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF TBD - ns tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF TBD - tr Clock rise time CL ≤ 30 pF - TBD tf Clock fall time CL ≤ 30 pF - TBD CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF TBD - ns tIH Input hold time CL ≤ 30 pF TBD - CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF - TBD ns tOH Output hold time CL ≤ 30 pF TBD - CMD, D outputs (referenced to CK) in SD default mode(2) 2. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. tOVD Output valid default time CL ≤ 30 pF - TBD ns tOHD Output hold default time CL ≤ 30 pF TBD - CK D, CMD (output) tOVD tOHD ai14888 Table 87. RTC characteristics Symbol Parameter Conditions Min Max -fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4- |
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