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ADF4001BCP Datasheet(PDF) 11 Page - Analog Devices

Part # ADF4001BCP
Description  200 MHz Clock Generator PLL
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4001BCP Datasheet(HTML) 11 Page - Analog Devices

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ADF4001
–11–
Table VI. Initialization Latch Map
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
F1
PD1
M1
M2
M3
F3
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
CPI3
CPI4
DB21
CURRENT
SETTING
2
TC3
TC2
TC1
DB22
DB23
F4
F5
RESERVED
CE PIN
PD2
PD1
MODE
0
X
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
101ASYNCHRONOUS POWER-DOWN
111SYNCHRONOUS POWER-DOWN
CPI6
CPI5
CP14
ICP (mA)
CPI3
CPI2
CPI1
2.7k
4.7k
10k
0
0
0
1.088
0.625
0.294
0
0
1
2.176
1.25
0.588
0
1
0
3.264
1.875
0.882
0
1
1
4.352
2.5
1.176
1
0
0
5.44
3.125
1.47
1
0
1
6.528
3.75
1.764
1
1
0
7.616
4.375
2.058
1
1
1
8.704
5.0
2.352
TIMEOUT
TC4
TC3
TC2
TC1
(PFD CYCLES)
00003
00017
0010
11
0011
15
0100
19
0101
23
0110
27
0111
31
1000
35
1001
39
1010
43
1011
47
1100
51
1101
55
1110
59
1111
63
F4
F5
FASTLOCK MODE
0
X
FASTLOCK DISABLED
1
0
FASTLOCK MODE 1
1
1
FASTLOCK MODE 2
F3
CHARGE PUMP OUTPUT
0
NORMAL
1
THREE-STATE
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
001DIGITAL LOCK DETECT
0
1
0
N DIVIDER OUTPUT
0
1
1
AVDD
1
0
0
R DIVIDER OUTPUT
1
0
1
N-CHANNEL OPEN-DRAIN
LOCK DETECT
110SERIAL DATA OUTPUT
1
1
1
DGND
PHASE DETECTOR
F2
POLARITY
0
NEGATIVE
1
POSITIVE
COUNTER
F1
OPERATION
0
NORMAL
1
R, N COUNTER
HELD IN RESET
X = DON’T CARE
XX



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