ADF4116 datasheet(18/20 Pages) AD

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ADF4116/ADF4117/ADF4118

–18–

REV. 0

APPLICATIONS SECTION

Local Oscillator for GSM Base Station Transmitter

Figure 26 shows the ADF4117/ADF4118 being used with a

VCO to produce the LO for a GSM base station transmitter.

The reference input signal is applied to the circuit at FREFIN

and, in this case, is terminated in 50

Ω. Typical GSM system

would have a 13 MHz TCXO driving the Reference Input

without any 50

Ω termination. In order to have a channel

spacing of 200 kHz (the GSM standard), the reference input

must be divided by 65, using the on-chip reference divider of

the ADF4117/ADF1118.

The charge pump output of the ADF4117/ADF1118 (Pin 2)

drives the loop ﬁlter. In calculating the loop ﬁlter component

values, a number of items need to be considered. In this example,

the loop ﬁlter was designed so that the overall phase margin for

the system would be 45 degrees. Other PLL system speciﬁca-

tions are given below:

KD = 1 mA

KV = 12 MHz/V

Loop Bandwidth = 20 kHz

FREF = 200 kHz

N = 4500

Extra Reference Spur Attenuation = 10 dB

All of these speciﬁcations are needed and used to come up with

the loop ﬁlter components values shown in Figure 27.

The loop ﬁlter output drives the VCO, which, in turn, is fed

back to the RF input of the PLL synthesizer and also drives

the RF Output terminal. A T-circuit conﬁguration provides

Ω matching between the VCO output, the RF output and

the RFIN terminal of the synthesizer.

In a PLL system, it is important to know when the system is in

lock. In Figure 26, this is accomplished by using the MUXOUT

signal from the synthesizer. The MUXOUT pin can be pro-

grammed to monitor various internal signals in the synthesizer.

One of these is the LD or lock-detect signal.

VCO190-902T

VCC

100pF

RFOUT

VDD

AVDD DVDD

ADF4117/

ADF4118

0.15nF

620pF

3.3k

715

FREFIN

1000pF 1000pF

MUXOUT

LOCK

DETECT

100pF

RFINA

RFINB

CLK

DATA

DECOUPLING CAPACITORS (10 F/10pF) ON AVDD, DVDD, VP OF THE

ADF4117/ADF4118 AND ON VCC OF THE VCO190-902T HAVE BEEN

OMITTED FROM THE DIAGRAM TO AID CLARITY.

FLO

10k

1.5nF

27k

REFIN

Figure 26. Local Oscillator for GSM Base Station

SHUTDOWN CIRCUIT

The attached circuit in Figure 27 shows how to shut down both

the ADF4116 family and the accompanying VCO. The ADG702

switch goes open circuit when a Logic 1 is applied to the IN

input. The low-cost switch is available in both SOT-23 and

micro SOIC packages.

DIRECT CONVERSION MODULATOR

In some applications a direct conversion architecture can be used

in base station transmitters. Figure 28 shows the combination

available from ADI to implement this solution.

The circuit diagram shows the AD9761 being used with the

AD8346. The use of dual integrated DACs such as the AD9761

with speciﬁed

±0.02 dB and ±0.004 dB gain and offset match-

ing characteristics ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The Local Oscillator (LO) is implemented using the ADF4117/

ADF4118. In this case, the OSC 3B1-13M0 provides the

stable 13 MHz reference frequency. The system is designed

for a 200 kHz channel spacing and an output center frequency

of 1960 MHz. The target application is a WCDMA base sta-

tion transmitter. Typical phase noise performance from this LO

is –85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is

driven in single-ended fashion. LOIN is ac-coupled to ground

with the 100 pF capacitor and LOIP is driven through the ac-

coupling capacitor from a 50

Ω source. An LO drive level of

between –6 dBm and –12 dBm is required. The circuit of Figure

28 gives a typical level of –8 dBm.

The RF output is designed to drive a 50

Ω load but must be

ac-coupled as shown in Figure 28. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power will

be around –10 dBm.

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