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ADF4116 Datasheet(PDF) 19 Page - Analog Devices

Part # ADF4116
Description  RF PLL Frequency Synthesizers
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4116 Datasheet(HTML) 19 Page - Analog Devices

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ADF4116/ADF4117/ADF4118
–19–
REV. 0
INTERFACING
The ADF4116 family has a simple SPI-compatible serial inter-
face for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table II for the Latch
Truth Table.
VDD
VP
AVDD DVDD
ADF4116/
ADF4117/
ADF4118
VP
10k
VCO
VCC
GND
18
100pF
100pF
18
18
RFOUT
715
16
2
1
6
5
8
FREFIN
51
100pF
34
9
100pF
RFINA
RFINB
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
FLO
CP
CE
POWER-DOWN CONTROL
VDD
S
IN
D
GND
LOOP
FILTER
ADG702
REFIN
Figure 27. Local Oscillator Shutdown Circuit
LOW-PASS
FILTER
RSET
ADF4118
VCO190-1960T
18
100pF
18
REFIN
100pF
RFINA
RFINB
CP
SERIAL
DIGITAL
NTERFACE
TCXO
OSC 3B1-13M0
100pF
51
18pF
1k
10k
6.8nF
18
RFOUT
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM FOR CLARITY.
AD9761
TXDAC
REFIO
FS ADJ
MODULATED
DIGITAL
DATA
QOUTB
IOUTA
IOUTB
QOUTA
LOW-PASS
FILTER
IBBP
QBBP
IBBP
QBBP
AD8346
LOIN
LOIP
VOUT
100pF
100pF
2k
0.1 F
100pF
680pF
Figure 28. Direct Conversion Transmitter Solution
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems which will have typical lock times in hun-
dreds of microseconds.



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