ADG465

–6–

REV. A

When a negative overvoltage is applied to the channel protector

circuit, the PMOS transistor enters a saturated mode of operation

the case of the positive overvoltage, the other MOS devices are

nonsaturated.

NEGATIVE

OVERVOLTAGE

(–20V)

NMOS

NMOS

(–13V)

PMOS

NEGATIVE

OVERVOLTAGE

(–20V)

SATURATED

NON-

SATURATED

NON-

SATURATED

Figure 9. Negative Overvoltage on the Channel Protector

The channel protector is also functional when the supply rails

are down (e.g., power failure) or momentarily unconnected

(e.g., rack system). This is where the channel protector has an

advantage over more conventional protection methods such as

microampere levels (see Figure 10).

(0V)

POSITIVE OR

NEGATIVE

OVERVOLTAGE

OFF

OFF

OFF

NMOS

NMOS

PMOS

Figure 10. Channel Protector Supplies Equal to Zero Volts

TRENCH ISOLATION

The MOS devices that make up the channel protector are

isolated from each other by an oxide layer (trench) (see Figure

11). When the NMOS and PMOS devices are not electrically

isolated from each other, there exists the possibility of “latchup”

caused by parasitic junctions between CMOS transistors. Latchup

is caused when P-N junctions that are normally reverse biased,

become forward biased, causing large currents to flow. This can

be destructive.

CMOS devices are normally isolated from each other by

Junction Isolation. In Junction Isolation, the N and P wells of the

CMOS transistors form a diode that is reverse biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A Silicon-Controlled Rectifier

(SCR) type circuit is formed by the two transistors, causing a

significant amplification of the current that, in turn, leads to

latchup. With Trench Isolation, this diode is removed; the result

is a latchup-proof circuit.

T

R

E

N

C

H

T

R

E

N

C

H

T

R

E

N

C

H

P-CHANNEL

N-CHANNEL

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

Figure 11. Trench Isolation