ADG731BCP datasheet(12/15 Pages) AD

12 / 15 page

–12–

REV. PrD

ADG725/ADG731

PRELIMINARY TECHNICAL DATA

GENERAL DESCRIPTION

The ADG725 and ADG731 are serially controlled, 32

channel and dual/differential 16 channel multiplexers re-

spectively.

POWER ON RESET

On power up of the device, all switches will be in the

OFF condition and the internal shift register is filled with

zeros and will remain so until a valid write takes place.

SERIAL INTERFACE

The ADG725 and ADG731 have a three wire serial inter-

face (

SYNC, SCLK, and DIN), which is compatible with

SPI, QSPI, MICROWIRE interface standards and most

DSP’s. Figure 1 shows the timing diagram of a typical

write sequence.

Data is written to the 8-bit shift register via DIN under

the control of the

SYNC and SCLK signals.

When

SYNC goes low, the input shift register is enabled.

An 8-bit counter is also enabled. Data from DIN is

clocked into the shift register on the falling edge of

SCLK. Figures 2 & 3 show the contents of the input shift

registers for these devices. When the part has received

eight clock cycles after

SYNC has been pulled low, the

switches are automatically updated with the new

configuration and the input shift register is disabled. With

SYNC held high, any further data or noise on the DIN

line will have no effect on the shift register.

The ADG725

CSA and CSB data bits allow the user the

flexibility to change the configuration of either or both

banks of the multiplexer.

ADG731BCP Datasheet(PDF) 12 Page - Analog Devices