ADN2850 datasheet(3/20 Pages) AD

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REV. B

ADN2850

–3–

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INTERFACE TIMING CHARACTERISTICS (apply to all parts)

5, 11

Clock Cycle Time (tCYC)t1

CS Setup Time

CLK Shutdown Time to

CS Rise

1tCYC

Input Clock Pulsewidth

t4 , t5

Clock Level High or Low

Data Setup Time

From Positive CLK Transition

Data Hold Time

From Positive CLK Transition

CS to SDO – SPI Line Acquire

CS to SDO – SPI Line Release

CLK to SDO Propagation Delay

t10

RP = 2.2 k

Ω, C

L < 20 pF

CS High Pulsewidth13

t12

CS High to CS High13

t13

4tCYC

RDY Rise to

CS Fall

t14

0ns

CS Rise to RDY Fall Time

t15

0.15

0.3

Read/Store to Nonvolatile EEMEM

t16

Applies to Command 2H, 3H, 9H

CS Rise to Clock Edge Setup

t17

Preset Pulsewidth (Asynchronous)

tPRW

Not Shown in Timing Diagram

Preset Response Time to Wiper Setting

tPRESP

PR Pulsed Low to Refresh

140

µs

Wiper Positions

FLASH/EE MEMORY RELIABILITY

Endurance

100

K Cycles

Data Retention

100

Years

NOTES

1 Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.

2 Typicals represent average readings at 258C and V

DD = 5 V.

3 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50

µA for V

DD = 2.7 V and IW ~ 400

µA for V

DD = 5 V.

4 Resistor terminals W and B have no limitations on polarity with respect to each other.

5 Guaranteed by design and not subject to production test.

6 Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V

DD/2.

7 Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.

8 P

DISS is calculated from (IDD

VDD) + (ISS

VSS).

9 Applies to photodiode of optical receiver.

10 All dynamic characteristics use V

DD = +2.5 V and VSS = –2.5 V.

11 See timing diagram for location of measured values. All input control voltages are specified with t

R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

Switching characteristics are measured using both VDD = 3 V and 5 V.

12 Propagation delay depends on value of V

DD, RPULL_UP, and CL. See Applications section.

13 Valid for commands that do not activate the RDY pin.

14 RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at T

A = –40

°C

and VDD < 3 V extends the save time to 35 ms.

15 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40

°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

16 Retention lifetime equivalent at junction temperature (T

J ) = 55

°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will

derate with junction temperature.

Specifications subject to change without notice.

The ADN2850 contains 16,000 transistors. Die size: 93 mil

103 mil, 10,197 sq mil.

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