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ADP3152 Datasheet(PDF) 7 Page - Analog Devices

Part # ADP3152
Description  5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP3152 Datasheet(HTML) 7 Page - Analog Devices

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ADP3152
–7–
REV. 0
expensive microprocessor from destruction. The crowbar func-
tion releases at approximately 50% of the nominal output volt-
age. For example, if the output is programmed to 2.0 V, but is
pulled up to 2.3 V or above, the crowbar will turn on the lower
MOSFET. If in this case the output is pulled down to less than
1.0 V, the crowbar will release, allowing the output voltage to
recover to 2.0 V.
Shutdown
The ADP3152 has a shutdown pin which is pulled logic low by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high externally to disable the
output drives.
Calculation of Component Values
The design parameters for a typical 300 MHz Pentium II appli-
cation (Figure 2) are as follows:
Input voltage: VIN = 5 V
Auxiliary input: VCC = 12 V
Output voltage: VO = 2.8 V
Maximum output current:
IOMAX = 14.2 Adc
Minimum output current:
IOMIN = 0.8 Adc
Static tolerance of the supply voltage for the processor core:
∆V
OST+ = 100 mV
∆V
OST– = –60 mV
Transient tolerance (for less than 2
µs) of the supply voltage for
the processor core when the load changes between the minimum
and maximum values with a di/dt of 30 A/
µs:
∆V
OTR+ = 130 mV
∆V
OTR– = –130 mV
Input current di/dt when the load changes between the mini-
mum and maximum values: less than 0.1 A/
µs
The above requirements correspond to Intel’s published power
supply requirements based on VRM 8.2 guidelines.
CT Selection for Operating Frequency
The ADP3152 uses a constant-off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high side N-channel MOSFET switch turns on, the voltage
across CT is reset to approximately 3.3 V. During the off time,
CT is discharged by a constant current of 65
µA to 2.3 V, that is
by 1 V. The value of the off time is calculated from the pre-
ferred continuous-mode operating frequency. Assuming a nomi-
nal operating frequency of fNOM = 200 kHz at an output voltage
of VO = 2.8 V, the corresponding off time is:
tOFF
= 1–
VO
V IN


1
f NOM
= 2.2 µs
The timing capacitor can be calculated from the equation:
CT
=
tOFF
×65 µA
1V
=143 pF
The converter operates at the nominal operating frequency only
at the above specified VO and at light load. At higher VO, and
heavy load, the operating frequency decreases due to the para-
sitic voltage drops across the power devices. The actual mini-
mum frequency at VO = 2.8 V is calculated to be 160 kHz (see
Equation 1 below). Where
IIN
is the input dc current (assuming an efficiency
of 90%, IIN = 9 A)
RIN
is the resistance of the input filter (estimated
value: 7 m
Ω)
RDS(ON)HSF
is the resistance of the high side MOSFET
(estimated value: 10 m
Ω)
RDS(ON)LSF
is the resistance of the low side MOSFET
(estimated value: 10 m
Ω)
RSENSE
is the resistance of the sense resistor
(estimated value: 7 m
Ω)
RL
is the resistance of the inductor (estimated
value: 6 m
Ω)
CO Selection—Determining the ESR
The selection of the output capacitor is driven by the required
ESR and capacitance CO. The ESR must be small enough that
both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage stay below the values
defined in the specification of the supplied microprocessor. The
capacitance, CO, must be large enough that the output is held
up while the inductor current ramps up or down to the value
corresponding to the new load current.
The total static tolerance of the Pentium II processor is 160 mV.
Taking into account the
±1% setpoint accuracy of the ADP3152,
and assuming a 0.5% (or 14 mV) peak-to-peak ripple, the al-
lowed static voltage deviation of the output voltage when the
load changes between the minimum and maximum values is
0.08 V. Assuming a step change of
∆I = I
OMAX–IOMIN = 13.4 A,
and allocating all of the total allowed static deviation to the
contribution of the ESR sets the following limit:
RE MAX
() = ESRMAX1 =
0.08
13. 4
= 5.9 mΩ
f MIN
=
1
tOFF
×
V IN – IIN RIN – IOMAX (RDS(ON)HSF
+ R
SENSE
+ R
L )–V O
V IN – IIN RIN – IOMAX (RDS(ON)HSF
+ R
SENSE
+ R
L – RDS(ON )LSF )
=160 kHz
(1)



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