REV. A

ADP3157

–10–

To correctly implement active voltage positioning, the low fre-

quency output impedance (i.e., the output resistance) of the

converter should be made equal to the maximum ESR of the

output capacitor array. This can be achieved by having a single

the pole frequency coincides with the ESR zero of the output

amplifier output pin be terminated by the parallel combination

of a resistor and capacitor. The required resistor value can be

calculated from the equation:

R

kRt

kRt

C

TOTAL

TOTAL

=

×

275

275

Ω

Ω –

where

Rt

kR

I

VV

TOTAL

CS

OMAX

HI

LO

=

××

16 4

.

–

Ω

and where the quantities 16.4

k

Ω and 275 kΩ are characteristics

of the ADP3157 and the value of the current sense resistor,

has already been determined as above.

the proper voltage positioning gain, the dc biasing of that resis-

tor would determine how the regulation band is centered (i.e.,

offset). Note that sometimes the specified regulation band is

asymmetrical with respect to the nominal VID voltage. With the

ADP3157, the offset is already considered as part of the design

procedure—no special provision is required. To accomplish the

amplifier output, with the lower resistor tied to ground and the

upper resistor to the 12 V supply of the IC. The values of these

resistors can be calculated using:

RR

V

V

UPPER

C

DIV

OS

=×

and

RR

V

VV

LOWER

C

OS

DIV

OS

=×

–

where

ommended 12 V), and

from the nominal VID-programmed value to the center of the

specified regulation window for the output voltage. (Note this

may be either positive or negative.) For clarification, that offset

is given by:

VV

V

VID

OUT OS

HI

LO

()

()–

=+

1

2

where

allowed for regulation.

Finally, the compensating capacitance is determined from the

equality of the pole frequency of the error amplifier gain and the

zero frequency of the impedance of the output capacitor:

C

C

ESR

Rt

COMP

O

TOTAL

=

×

Trade-Offs Between DC Load Regulation and AC Load

Regulation

Casual observation of the circuit operation—e.g., with a voltmeter

—would make it appear that the dc load regulation appears

to be rather poor compared to a conventional regulator. This

would be especially noticeable under very light or very heavy

loads where the voltage is “positioned” near one of the extremes

of the regulation window rather than near the nominal center

value. It must be noted and understood that this low gain char-

acteristic (i.e., loose dc load regulation) is inherently required to

allow improved transient containment (i.e., to achieve tighter ac

load regulation). That is, the dc load regulation is intentionally

sacrificed (but kept within specification) in order to minimize

the number of capacitors required to contain the load transients

produced by the CPU.

LAYOUT AND COMPONENT PLACEMENT GUIDELINES

The following guidelines are recommended for optimal perfor-

mance of a switching regulator in a PC system:

General Recommendations

1.

For best results, a four-layer (minimum) PCB is recom-

mended. This should allow the needed versatility for con-

trol circuitry interconnections with optimal placement, a

signal ground plane, power planes for both power ground

and the input power (e.g., 5 V), and wide interconnection

traces in the rest of the power delivery current paths. Each

square unit of 1 ounce copper trace has a resistance of

~0.53 mW at room temperature.

2.

Whenever high currents must be routed between PCB

layers, vias should be used liberally to create several parallel

current paths so that the resistance and inductance intro-

duced by these current paths is minimized and the via cur-

rent rating is not exceeded.

3.

The power and ground planes should overlap each other as

little as possible. It is generally easiest (although not neces-

sary) to have the power and signal ground planes on the

same PCB layer. The planes should be connected nearest

to the first input capacitor where the input ground current

flows from the converter back to the power source (e.g.,

5 V).

V

R

Rt

VV

Rt

k

V

Rt

k

RI

OS

C

TOTAL

OUT OS

TOTAL

TOTAL

CS OMAX

=×

+























 +

















08

136

17

275

6

.

.

–.

()

ΩΩ

(2)