ADP3412

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REV. 0

THEORY OF OPERATION

The ADP3412 is a dual MOSFET driver optimized for driving

two N-channel MOSFETs in a synchronous buck converter

topology. A single PWM input signal is all that is required to

properly drive the high-side and the low-side FETs. Each driver

is capable of driving a 3 nF load with only a 20 ns transition time.

A more detailed description of the ADP3412 and its features

follows. Refer to the general application circuit in Figure 1.

Low-Side Driver

MOSFETs. The maximum output resistance for the driver is

5

Ω for both sourcing and sinking gate current. The low output

resistance allows the driver to have 20 ns rise and fall times into

a 3 nF load. The bias to the low-side driver is internally con-

nected to the VCC supply and PGND.

The driver’s output is 180 degrees out of phase with the PWM

input.

High-Side Driver

N-channel MOSFET. The maximum output resistance for the

driver is 5

Ω for both sourcing and sinking gate current. The

low output resistance allows the driver to have 20 ns rise and fall

times into a 3 nF load. The bias voltage for the high-side driver

is developed by an external bootstrap supply circuit, which is

connected between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

is at ground, so the bootstrap capacitor will charge up to VCC

through D1. When the PWM input goes high, the high-side

driver will begin to turn ON the high-side MOSFET, Q1, by

enough gate-to-source voltage to hold Q1 ON. To complete the

cycle, Q1 is switched OFF by pulling the gate down to the volt-

age at the SW pin. When the low-side MOSFET, Q2, turns

ON, the SW pin is pulled to ground. This allows the bootstrap

capacitor to charge up to VCC again. The high-side driver’s

output is in phase with the PWM input.

Overlap Protection Circuit

The Overlap Protection Circuit (OPC) prevents both of the

main power switches, Q1 and Q2, from being ON at the same

time. This is done to prevent shoot-through currents from flow-

ing through both power switches and the associated losses that

can occur during their ON-OFF transitions. The Overlap Pro-

tection Circuit accomplishes this by adaptively controlling the

delay from Q1’s turn OFF to Q2’s turn ON, and by externally

setting the delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF

and Q2’s turn ON, the overlap circuit monitors the voltage at

the SW pin. When the PWM input signal goes low, Q1 will begin

to turn OFF (after a propagation delay), but before Q2 can turn

ON, the overlap protection circuit waits for the voltage at the SW

fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage

on the SW pin to reach 1 V, the overlap protection circuit ensures

that Q1 is OFF before Q2 turns on, regardless of variations in

temperature, supply voltage, gate charge, and drive current.

To prevent the overlap of the gate drives during Q2’s turn OFF

and Q1’s turn ON, the overlap circuit provides a programmable

delay that is set by a capacitor on the DLY pin. When the PWM

input signal goes high, Q2 will begin to turn OFF (after a propa-

gation delay), but before Q1 can turn ON the overlap protection

circuit waits for the voltage at DRVL to drop to around 10% of

VCC. Once the voltage at DRVL has reached the 10% point,

the overlap protection circuit will wait for a 20 ns typical propa-

gation delay plus an additional delay based on the external

of delay. Once the programmable delay period has expired, Q1

will begin turn ON. The delay allows time for current to com-

mutate from the body diode of Q2 to an external Schottky diode,

which allows turnoff losses to be reduced. Although not as fool-

proof as the adaptive delay, the programmable delay adds a

safety margin to account for variations in size, gate charge, and

internal delay of the external power MOSFETs.

APPLICATION INFORMATION

Supply Capacitor Selection

For the supply input (VCC) of the ADP3412, a local bypass

capacitor is recommended to reduce the noise and to supply some

of the peak currents drawn. Use a 1

µF, low ESR capacitor.

Multilayer ceramic chip (MLCC) capacitors provide the best

combination of low ESR and small size and can be obtained from

the following vendors:

Murata

GRM235Y5V106Z16

www.murata.com

Taiyo-

Yuden

EMK325F106ZF

www.t-yuden.com

Tokin

C23Y5V1C106ZP

www.tokin.com

Keep the ceramic capacitor as close as possible to the ADP3412.

Bootstrap Circuit

a Schottky diode, as shown in Figure 1. Selection of these com-

ponents can be done after the high-side MOSFET has been

chosen.

The bootstrap capacitor must have a voltage rating that is able

to handle the maximum battery voltage plus 5 volts. A minimum

50 V rating is recommended. The capacitance is determined

using the following equation:

C

Q

V

BST

GATE

BST

=

∆

and

∆V

drive. For example, the IRF7811 has a total gate charge of about

20 nC. For an allowed droop of 200 mV, the required boot-

strap capacitance is 100 nF. A good quality ceramic capacitor

should be used.

A Schottky diode is recommended for the bootstrap diode due

to its low forward drop, which maximizes the drive available for

the high-side MOSFET. The bootstrap diode must have a mini-

mum 40 V rating to withstand the maximum battery voltage

plus 5 V. The average forward current can be estimated by:

MAX

GATE

F(AVG)

f

Q

I

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