ADP3801 datasheet(15/20 Pages) AD

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ADP3801/ADP3802

–15–

REV. 0

The efficiency of this circuit is shown in Figure 26 for a charge

current of 4 Amps. As expected, the efficiency increases with the

output voltage, up to a maximum of 92% at 12.6 V.

OUTPUT – Volts

910

VCC = 15V

ICHARGE = 4 AMP

FREQ = 200kHz

FREQ = 500kHz

100

Figure 26. Efficiency for ICHARGE = 4.0 Amp

Figure 27 shows the output voltage transient when a battery

load is snapped off. The output is charging a battery (which is

currently discharged to 5 V) at 4.0 A when the battery is re-

moved. The high charge current causes the output voltage to

quickly increase and exceed the final battery voltage. However,

the overvoltage comparator quickly controls the output and only

a small overshoot results. When the battery is returned to the

circuit, VBAT is pulled back down to the battery’s voltage.

TIME – ms

2.00V

10V

12V

14V

CH1

M50.0ms

CH 1

10.0V

VBAT = 12.6V

ICHARGE = 4 AMP

VCC = 15V

50ms/DIV

Figure 27. Output Voltage Transient Due to Battery Snap

Off

The behavior of the circuit when it is powered on with a dead

battery inserted is important to check to make sure that the

charger does not exhibit irregular behavior during power-up. In

this case, the ADP3801 needs to regulate the output current to

4.0 A. Figure 28 shows the average Si4463 source current

under such a condition. When the input power is applied to the

charger, the source current ramps up in a controlled manner

due to the ADP3801’s soft start.

10V

15V

VCC = 15V

TA = +25 C

ICHARGE = 4 Amps

20ms/DIV

ICHARGE (AVERAGE)

VCC

Figure 28. Source Current Due to Input Turn-On

Feedback Loop Compensation Design

The ADP3801 and ADP3802 have two separate feedback loops,

the current control loop and the voltage control loop. Each loop

must be compensated properly so that the circuit is stable dur-

ing the entire charging cycle of a battery including the case where

no battery is present. A series RC from the COMP pin to ground

provides pole/zero compensation for both loops. The circuit in

Figure 24 is properly compensated for the ADP3801 and

ADP3802 and can be used as is.

Figure 29 shows a typical ac model of the ADP3801/ADP3802.

The current loop and voltage loop are comprised of voltage

controlled current sources (GM stages). The gains given in the

schematic and the impedance at the COMP node are typical

values for both the ADP3801 and ADP3802. This model can be

used to simulate the small signal ac behavior of the part using a

SPICE-based simulator when paired with an ac model of a buck

regulator. However, transient and dc behavior is not modeled

with this model. The GM stages are actually modeled using the

“Table” component in PSpice, which limits the dc levels to ease

dc convergence. The coefficients on the schematic give the table

coefficients. The input resistors (R1 and R2) are currently set

for a 4.2 V final battery voltage. Use the accompanying table to

adjust R1 and R2 for the other voltage options. Doing so is

important to properly set the voltage loop gain.

GM2

CS+

1.65V

gm = 8E – 3

(–12.5m, –200E – 6) (12.5m,0)

100 A

GM3

GM1

CS–

4.2V

173k

112k

8.4V

229k

56k

12.6V

247.7k

37.3k

VBAT

100k

112k

173k

VBAT

gm = 1.6E – 3

(–62.5m, –200E – 6) (62.5m,0)

GAIN = 1V/V

OUT

gm = 1E – 4

(0,0) (0.2, 20E – 6)

ISET

Figure 29. AC Behavioral SPICE Model for the ADP3801

and ADP3802

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