ADP3811AR datasheet(16/16 Pages) AD

16 / 16 page

ADP3810/ADP3811

–16–

REV. 0

Step 14. Calculate value of RC2 to realize GLOSS:

Assuming that CC2 is a short, RC2 forms a resistor divider with

R3, reducing the loop gain. To calculate RC2, simply set the resis-

tor ratio to give an attenuation of 25.5 dB, which is a loss of 1/20.

RC2 =

R 3

−1

= 1kΩ

To provide some margin in the circuit for gain fluctuations in

the various stages, the final value of RC2 was adjusted down to

300

Ω.

Step 15. Calculate the value of CC2:

To maintain high dc gain, a capacitor, CC2, is connected in se-

ries with RC2. The zero provided by this RC network should be

close to fCI to provide a phase boost at crossover:

f Z2 ≈1.9 kHz

CC2 =

π× f

Z2 × RC2

π×1.9kHz × 300 Ω

≈ 200 nF

The pole frequency due to CC2 and R3 can now be calculated

as:

f P2 =

π× C

C2 × R 3

= 40 Hz

Step 16. Check the current loop phase margin:

M = 180 − arc tan

f CI

f P2









+ arc tan

f CI

f Z2









− arc tan

f CI

f PM









+arc tan

f CI

f ZM









+ arc tan

f CI

f P1









+ arc tan

f CI

f Z3









M ≈ 115°

The above formula subtracts the phase of each pole and adds

the phase of each zero. The poles and zeros come in pairs, fP2/fZ2

calculated in Step 15 from CC2/RC2; fPM/fZM calculated in Step 10

due to the output filter cap; and fP1/fZ3 due to CC1/RC1. fP1 is

the same pole that was calculated in Step 9, and fZ3 needs to be

recalculated with the addition of the internal 200

Ω resistor as

follows:

f Z3 =

π× C

C1 × RC1 + R6

()

= 78 Hz

The final phase margin of 115

° is more than adequate for a

stable current loop. In reality, higher order parasitic poles reduce

the phase margin to significantly less than 115

° for a 1.9 kHz

crossover. The same was not the case for the voltage loop be-

cause the cross over frequency of 100 Hz was well below the

parasitic poles.

A PSpice analysis of the resulting loop gain and phase for the

values calculated is shown in Figure 33.

FREQUENCY – Hz

–50

0.01

100k

0.1

100

10k

100

180

100

0dB CROSSOVER

PHASE MARGIN = 105

Figure 33. Current Loop Gain/Phase Plots

8-Lead Small Outline IC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0196 (0.50)

0.0099 (0.25)

x 45

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

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