| Electronic Components Datasheet Search |
|
ADSP2181 Datasheet(PDF) 14 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADSP2181 Datasheet(HTML) 14 Page - Analog Devices |
|
14 / 32 page ![]() REV. D ADSP-2181 –14– Parameter Min Max Unit Clock Signals and Reset Timing Requirements: tCKI CLKIN Period 50 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns Switching Characteristics: tCKL CLKOUT Width Low 0.5tCK – 7 ns tCKH CLKOUT Width High 0.5tCK – 7 ns tCKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement: tRSP RESET Width Low 5tCK 1 ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKOH tCKI tCKIH tCKIL tCKH tCKL tMH tMS CLKIN CLKOUT PF(2:0) * RESET *PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 8. Clock Signals |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |