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ADSP2181 Datasheet(PDF) 16 Page - Analog Devices |
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ADSP2181 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 32 page ![]() REV. D ADSP-2181 –16– Parameter Min Max Unit Bus Request/Grant Timing Requirements: tBH BR Hold after CLKOUT High1 0.25tCK + 2 ns tBS BR Setup before CLKOUT Low1 0.25tCK + 17 ns Switching Characteristics: tSD CLKOUT High to xMS, 0.25tCK + 10 ns RD, WR Disable tSDB xMS, RD, WR Disable to BG Low 0 ns tSE BG High to xMS, RD, WR Enable 0 ns tSEC xMS, RD, WR Enable to CLKOUT High 0.25tCK – 4 ns tSDBH xMS, RD, WR Disable to BGH Low2 0ns tSEH BGH High to xMS, RD, WR Enable2 0ns NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. CLKOUT tSD tSDB tSE tSEC tSDBH tSEH tBS BR tBH CLKOUT PMS, DMS BMS, RD WR BG BGH Figure 10. Bus Request–Bus Grant |
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