ADT7316/7317/7318

–29–

REV. PrN

PRELIMINARY TECHNICAL DATA

The following sections describe in detail how to use these

interfaces.

I

Like all I

has an 7-bit serial address. The four MSBs of this address

for the ADT7316/7317/7318 are set to 1001. The three

LSBs are set by pin 11, ADD. The ADD pin can be con-

figured three ways to give three different address options;

low, floating and high. Setting the ADD pin low gives a

serial bus address of 1001 000, leaving it floating gives the

address 1001 010 and setting it high gives the address

1001 011.

There is a programmable SMBus timout. When this is

enabled the SMBus will timeout after 25 ms of no activity.

To enable it, set Bit 6 of Control Configuration 2 regis-

ter. The power-up default is with the SMBus timeout

disabled.

The ADT7316/17/18 supports SMBus Packet Error

Checking (PEC) and it’s use is optional. It is triggered by

supplying the extra clocks for the PEC byte. The PEC is

calculated using CRC-8. The Frame Clock Sequence

(FCS) conforms to CRC-8 by the polynominal :

C(x) = x

Consult SMBus specification for more information.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a

START condition, defined as a high to low transition

on the serial data line SDA whilst the serial clock line

SCL remains high. This indicates that an address/data

stream will follow. All slave peripherals connected to

the serial bus respond to the START condition, and

shift in the next 8 bits, consisting of a 7-bit address

(MSB first) plus a R/

W bit, which determines the direc-

tion of the data transfer, i.e. whether data will be writ-

ten to or read from the slave device.

The peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low

during the low period before the ninth clock pulse,

known as the Acknowledge Bit. All other devices on the

bus now remain idle whilst the selected device waits for

data to be read from or written to it. If the R/

W bit is a

0 then the master will write to the slave device. If the

R/

W bit is a 1 the master will read from the slave de-

vice.

2. Data is sent over the serial bus in sequences of 9 clock

pulses, 8 bits of data followed by an Acknowledge Bit

from the receiver of data. Transitions on the data line

must occur during the low period of the clock signal

and remain stable during the high period, as a low to

high transition when the clock is high may be inter-

preted as a STOP signal.

3. When all data bytes have been read or written, stop

conditions are established. In WRITE mode, the master

will pull the data line high during the 10th clock pulse

to assert a STOP condition. In READ mode, the mas-

ter device will pull the data line high during the low

period before the 9th clock pulse. This is known as No

Acknowledge. The master will then take the data line

low during the low period before the 10th clock pulse,

then high during the 10th clock pulse to assert a STOP

condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix

read and write in one operation, because the type of opera-

tion is determined at the beginning and cannot subse-

quently be changed without starting a new operation.

WRITING TO THE ADT7316/7317/7318

Depending on the register being written to, there are two

different writes for the ADT7316/7317/7318. It is not

possible to do a block write to this part i.e no I

increment.

Writing to the Address Pointer Register for a subsequent

read.

In order to read data from a particular register, the Ad-

dress Pointer Register must contain the address of that

register. If it does not, the correct address must be written

to the Address Pointer Register by performing a single-

byte write operation, as shown in Figure 17. The write

operation consists of the serial bus address followed by the

address pointer byte. No data is written to any of the data

registers. A read operation is then performed to read the

register.

Figure 21. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation

D7

SCL K

D

IN

D6

D5

D4

D3

D2

D1

D6

D5

D4

D3

D2

D1

D0

START

WRITE COMMAND

REGISTER ADDRESS

18

1

8

CS

D0

D7

STOP