ADV7128

REV. 0

–7–

DAC

Z

O

= 75

Ω

(CABLE)

Z

S

= 75

Ω

(SOURCE

TERMINATION)

AD848

+V

S

0.1

µF

0.1

µF

I

OUT

75

Ω

2

7

6

4

3

Z

2

Z

L

= 75

Ω

(MONITOR)

GAIN (G) = 1+

–V

S

Z

1

Z

1

Z

2

Figure 6. AD848 As an Output Buffer

PC Board Layout Considerations

The ADV7128 is optimally designed for lowest noise perfor-

mance, both radiated and conducted noise. To complement the

excellent noise performance of the ADV7128 it is imperative

that great care be given to the PC board layout. Figure 7 shows

a recommended connection diagram for the ADV7128.

The layout should be optimized for lowest noise on the

ADV7128 power and ground lines. This can be achieved by

shielding the digital inputs and providing good decoupling. The

minimized so as to minimize inductive ringing.

Ground Planes

The ADV7128 and associated analog circuitry, should have a

separate ground plane referred to as the analog ground plane.

This ground plane should connect to the regular PCB ground

plane at a single point through a ferrite bead, as illustrated in

Figure 7. This bead should be located as close as possible

(within 3 inches) to the ADV7128.

The analog ground plane should encompass all ADV7128

ground pins, voltage reference circuitry, power supply bypass

circuitry, the analog output traces and any output amplifiers.

The regular PCB ground plane area should encompass all the

digital signal traces, excluding the ground pins, leading up to

the ADV7128.

Power Planes

The PC board layout should have two distinct power planes,

one for analog circuitry and one for digital circuitry. The analog

sociated analog circuitry. This power plane should be connected

a ferrite bead, as illustrated in Figure 7. This bead should be lo-

cated within three inches of the ADV7128.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7128 power pins, voltage reference circuitry

and any output amplifiers.

The PCB power and ground planes should not overlay portions

of the analog power plane. Keeping the PCB power and ground

planes from overlaying the analog power plane will contribute to

a reduction in plane-to-plane noise coupling.

Supply Decoupling

Noise on the analog power plane can be further reduced by the

use of multiple decoupling capacitors. (See Figure 7.)

Optimum performance is achieved by the use of 0.1

µF ceramic

decoupled to ground. This should be done by placing the ca-

pacitors as close as possible to the device with the capacitor

leads as short as possible, thus minimizing lead inductance.

GND

RSET

I

OUT

GROUND

ADV7128

C3

0.1

µF

C5

0.1

µF

Z1

(AD589)

R1

75

Ω

C1

33

µF

C2

10

µF

COMP

C6

0.1

µF

ANALOG POWER PLANE

V

AA

V

REF

L2 (FERRITE BEAD)

D0

D9

CLOCK

VIDEO

OUTPUT

VIDEO

DATA

INPUTS

ANALOG GROUND PLANE

C4

0.1

µF

560

Ω

L1 (FERRITE BEAD)

CC

+5V (V

)

VENDOR PART NUMBER

FAIR-RITE 274300111 OR

MURATA BL01/02/03

DALE CMF-55C

DALE CMF-55C

ANALOG DEVICES AD589JH

COMPONENT

C1

C2

C3, C4, C5,C6

L1, L2

R1

R

SET

Z1

DESCRIPTION

33

µF TANTALUM CAPACITOR

10

µF TANTALUM

0.1

µF CERAMIC CAPACITOR

FERRITE BEAD

75

Ω 1% METAL FILM RESISTOR

560

Ω 1% METAL FILM RESISTOR

1.235V VOLTAGE REFERENCE

Figure 7. ADV7128 Typical Connection Diagram and Component List