ADV7128 datasheet(4/8 Pages) AD

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ADV7128

REV. 0

–4–

ABSOLUTE MAXIMUM RATINGS

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V

Voltage on Any Digital Pin . . . . . . GND –0.5 V to VAA +0.5 V

Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C

Storage Temperature (TS) . . . . . . . . . . . . . . . –65

°C to +150°C

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150

°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300

°C

Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . . +220

°C

IOUT to GND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA

NOTES

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

1Analog Output Short Circuit to any Power Supply or Common can be of an

indefinite duration.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

ADV7128

SET

COMP

GND

CLOCK

OUT

V REF

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADV7128 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

PIN FUNCTION DESCRIPTION

Mnemonic

Function

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and

BLANK

pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven

by a dedicated TTL buffer.

D0–D9

Data inputs (TTL compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.

Unused data inputs should be connected to either the regular PCB power or ground plane.

IOUT

Current output. This high impedance current source is capable of directly driving a doubly terminated 75

Ω

coaxial cable.

RSET

Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the

full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.

The relationship between RSET and the full-scale output current on IOUT is given by:

IOUT (mA) = 7,969

VREF(V)/RSET(Ω)

COMP

Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1

µF ceramic capacitor

must be connected between COMP and VAA.

VREF

Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an exter-

nal resistor divider network is not recommended. A 0.1

µF decoupling ceramic capacitor should be connected be-

tween VREF and VAA.

VAA

Analog power supply (5 V

± 5%). All V

AA pins on the ADV7128 must be connected.

GND

Ground. All GND pins must be connected.

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