ADV7196A datasheet(28/36 Pages) AD

28 / 36 page

REV. 0

ADV7196A

–28–

MODE REGISTER 2

MR1 (MR27–MR20)

(Address (SR4–SR0) = 02H)

Figure 53 shows the various operations under the control of Mode

MR2 BIT DESCRIPTION

Y Delay (MR20–MR22)

With these bits it is possible to delay the Y signal with respect to

the falling edge of the horizontal sync signal by up to four pixel

clock cycles. Figure 52 demonstrates this facility.

Color Delay (MR23–MR25)

With theses bits it is possible to delay the color signals with respect

to the falling edge of the horizontal sync signal by up to four pixel

clock cycles. Figure 52 demonstrates this facility.

Reserved (MR26–MR27)

A “0” must be written to these bits.

MAX DELAY

NO DELAY

MAX DELAY

PrPb DELAY

Y DELAY

Y OUTPUT

PrPb OUTPUTS

Figure 52. Y and Color Delay

MODE REGISTER 3

MR3 (MR37–MR30)

(Address (SR4-SR0) = 03H)

Figure 54 shows the various operations under the control of Mode

MR3 BIT DESCRIPTION

HDTV Enable (MR30)

When this bit is set to “1” the ADV7196A reverts to HDTV

mode. When set to “0” the ADV7196A reverts to Progressive

Scan mode (PS mode).

Reserved (MR31–MR32)

A “0” must be written to these bits.

DAC A Control (MR33)

Setting this bit to “1” enables DAC A, otherwise this DAC is

powered down.

DAC B Control (MR34)

Setting this bit to “1” enables DAC B, otherwise this DAC is

powered down.

DAC C Control (MR35)

Setting this bit to “1” enables DAC C, otherwise this DAC is

powered down.

Reserved (MR36–MR37)

A “0” must be written to these bits.

MR21

MR27

MR22

MR24

MR25

MR23

MR20

MR26

MR25

MR24

MR23

0 PCLK

1 PCLK

2 PCLK

3 PCLK

4 PCLK

COLOR DELAY

MR22

MR21

MR20

0 PCLK

1 PCLK

2 PCLK

3 PCLK

4 PCLK

Y DELAY

MR27–MR26

ZERO MUST BE

WRITTEN TO

THESE BITS

Figure 53. Mode Register 2

MR37

MR32

MR34

MR36

ZERO MUST BE

WRITTEN TO

THESE BITS

MR37–MR36

MR34

POWER-DOWN

NORMAL

DAC B CONTROL

MR35

POWER-DOWN

NORMAL

DAC C CONTROL

MR33

ZERO MUST BE

WRITTEN TO

THESE BITS

MR32–MR31

MR31

MR30

DISABLE

ENABLE

HDTV ENABLE

MR30

MR33

POWER-DOWN

NORMAL

DAC A CONTROL

Figure 54. Mode Register 3

ADV7196A Datasheet(PDF) 28 Page - Analog Devices

ADV7196A Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL