SDZ

Hi-Z

TTL

Buffer

Gain

Control

GAIN

OUTP_FB

IN+

IN–

Gain

Control

OUTPN_FB

FAULTZ

SYNC

GAIN/SLV

FS<2:0>

AVCC

PVCC

LDO

Regulator

GND

AVDD

GVDD

Ramp

Generator

Biases and

References

Startup Protection

Logic

SC Detect

Thermal

Detect

UVLO/OVLO

GND

BSN

OUTP

GND

OUTN

OUTN_

FB

BSP

OUTP_FB

PVCC

GVDD

PVCC

Gate

Drive

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation Select

+

–

+

–

+

–

+

–

+

–

+

–

Thermal

Pad

PVCC

GVDD

DRV595

SLOS808 – DECEMBER 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM BLOCK DIAGRAM

2

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