LTC6930 datasheet(19/28 Pages) LINER

19 / 28 page

LTC6995-1/LTC6995-2

699512f

For more information www.linear.com/6995

applicaTions inForMaTion

Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate

Gated Oscillators

The reset input (RST) clears all internal dividers so that,

when released, the output will start clocking with a full

programmed period. This edge can be used to gate the

output ON and OFF at a known starting point for the clock.

Circuits which count clock cycles for further timing pur-

poses will always have an accurate count of full cycles

until reset. The output clock is always at 50% duty cycle

and the period of each cycle can range from 1ms to 9.5

hours. Depending on the polarity bit selection the output

clock can start high or low as shown in Figure 18.

Self-Resetting Circuits

TheRSTpinhashysteresistoaccommodateslow-changing

inputvoltages.Furthermore,thetrippointsareproportional

to the supply voltage (see Note 6 and the RST Threshold

Voltage vs Supply Voltage curve in Typical Performance

Characteristics). This allows an RC time constant at the

RST input to generate a delay that is nearly independent

of the supply voltage.

699512 F18

OUT

POL = 0

OUT

POL = 1

1/2 tOUT

RST

LTC6995-2

ACTIVE LOW RESET

RST RISING EDGE STARTS THE CLOCK

OUT

POL = 0

OUT

POL = 1

1/2 tOUT

RST

LTC6995-1

ACTIVE HIGH RESET

RST FALLING EDGE STARTS THE CLOCK

A simple application of this technique allows the LTC6995

output to reset itself, producing a well-controlled pulse

once each cycle. Figures 19a and 19b show circuits that

produceapproximately1µspulsesonceaminute.Theonly

difference is the version of LTC6995 used and the POL

bit setting, which controls whether the pulse is positive

or negative.

Voltage Controlled Frequency

Withoneadditionalresistor,theLTC6995outputfrequency

can be manipulated by an external voltage. As shown in

Figure 20, voltage VCTRL sources/sinks a current through

RVCO to vary the ISET current, which in turn modulates the

output frequency as described in Equation (3).

MHzk

OUT

DIV

VCO

SET

CTRL

150

1024

•

••

•–

Ω

EET









(3)

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