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OR3LP26B Datasheet(PDF) 100 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 100 Page - Agere Systems |
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100 / 184 page  ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 100 Lucent Technologies Inc. Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) Table 37. Quad-Port Master Read, Duplicate Burst Length and 16-Bit Address * mrlastcycn is 0 on the last data DWORD transfer. Table 38. Quad-Port Master Read, Specified Burst Length and 64-Bit Address * mrlastcycn is 0 on the last data DWORD transfer. mstatecntr Next State of mstatecntr Description Bus maenn mwlastcycn mrlastcycn mrdataenn 00 Idle — 1 1 1 1 0 4 BE[7:0], Address[15:0] mwdata[35:0] 0 0 1 1 4 5 or 0 Data[31:0] mrdata[31:0] 1 1 1 0 5 4 or 0 Data[63:32] mrdata[31:0] 1 1 0* 0 mstatecntr Next State of mstatecntr Description Bus maenn mwlastcycn mrlastcycn mrdataenn 00 Idle — 1 1 1 1 0 1 or 4 BE[7:0], Burst Length mwdata[35:0] 0 1 1 1 1 2 or 4 Address[31:0] mwdata[31:0] 0 1 1 1 2 4 Address[63:32] mwdata[31:0] 0 0 1 1 4 5 or 0 Data[31:0] mrdata[31:0] 1 1 1 0 5 4 or 0 Data[63:32] mrdata[31:0] 1 1 0* 0 |
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